Re: SCR triggering for high current inductive loads


"Fred Bloggs" <nospam@xxxxxxxxxx> wrote in message
news:449432D6.3080301@xxxxxxxxxxxxx

[snip]

I have used several designs for firing circuits. Originally we used
commercially available controllers which used high frequency pulses to
fire the gates, but quite often we would see waveform distortion because
the current was not enough to keep the SCR in conduction. I designed
several circuits that used DC for the gates, and made sure that the
current was applied only when the anode had a positive voltage. However,
because of the inductive load, there was current still flowing when the
gate current was turned off, and distortion was seen.

Finally, about ten years ago, I designed a simpler board which kept gate
current on continuously, and these boards have been used in hundreds of
test sets with no apparent problems related to the gate drive. I use a
simple constant current source with a PNP transistor and a 2.0 ohm
resistor, and diodes, which limits the current to one junction drop
(0.6V) on 2 ohms, or about 300 mA. It is sourced from about 12 VDC.

[snip]

Your description is too nebulous to understand the setup with any
certainty, like for example your mention of distortion while firing at
70o phase angles...makes no sense. You might spring for a technical
writer.


I could have written more details, but the post was too long already. With
a partially inductive load, the phase angle of current lags the voltage by
up to 90 degrees. We have determined that 70 degrees is characteristic for
the case of a shunt placed across the output connections (essentially a
bolted short), and we examine the waveform with an analyzer using the
millivolt drop. This is also how we calibrate the unit. We have also
analyzed the waveform with the shunt in series with the test loads, which
may be any one of thousands of different circuit breakers, each with
varying amounts of inductance. Some show evidence of saturation, so the
waveform is distorted with characteristic peaks and high crest factor.

The initial waveform into the circuit breaker must be such that the first
half-cycle is about the same as those proceeding it. If it is much lower,
the instantaneous trip element will ignore it, and will act upon the next
half-cycle, which will actually be higher than those proceeding it. As the
measurement circuit reads the entire waveform and performs a true-RMS
computation on it, this creates a timing error of about 1/2 cycle and a
corresponding measurement error. The new SCR board will be capable of
adjusting the initial firing angle to produce the best waveform possible.
Some of this may be incomprehensible to someone who is not familiar with
circuit breaker testing.

The distortion I was referring to occurred mostly on test sets where the
voltage applied to the SCRs was low (perhaps 10-20 VAC), and the current
also fairly low (5 amperes or so). These are large SCRs, and especially for
older ones, the holding current is probably several amperes. There is some
unavoidable distortion at these levels due to the 1 or 2 volt drop on the
SCRs, but we were seeing distortion that indicated the SCR was dropping out
of conduction well before the normal zero crossing. The loss of conduction
coincided approximately with the removal of gate drive at the zero crossing
of voltage, which occurred about 70 degrees before the zero crossing of
current. When the current dropped below holding current, the SCR went out
of conduction, causing a drop in current. This was sometimes followed by
one or more current spikes, due to inductive kick and dV/dT triggering.
Using DC for the gate drive solved this problem.

However, that could explain some problems that we have seen when we try to
obtain the exact number of half-cycles. If the gate drive is removed too
long before the end of the current, an effect as described above could
occur. If it is removed after the zero crossing, then the SCR might be
triggered and conduct for the following half-cycle. It may be critical to
detect the current zero crossings and remove gate drive at the optimum
time.

I hope this explains it.

Thanks,

Paul


.

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