Re: Separate pulses from edges?

John Fields <jfields@xxxxxxxxxxxxxxxxxxxxx> wrote:

On 25 Jun 2006 10:18:11 -0700, "John O'Flaherty"
<quiasmox@xxxxxxxxx> wrote:


John Fields wrote:
On 25 Jun 2006 08:31:50 -0700, "John O'Flaherty"
<quiasmox@xxxxxxxxx> wrote:


Now I see why you wanted those signals to go into the set/reset inputs
of a toggle flip-flop. This being your target, you might use John
Popelish's idea of a single time constant with an xor gate to get both
change signals on a single line. These could be used to reset an R/S
flip-flop. The set for that flip-flop would be your radio signal, and
the output of that flip-flop would go to another xor in the package to
reverse the current sense of the lights. That is, the radio signal
would turn the lights off if they would otherwise be on, on if they
would be off. Either normal day/night transition would reset the
sense-reversing flip-flop. The advantage of doing it this way is using
only a single time constant, with both signals on one line, and using a
single pair of gates for the R-S flip flop.

---
The disadvantage, however, is that it won't do what he wants it to
do, which is to turn ON at dusk automatically, (subject to an RF
override) and turn off at dawn automatically, also subject to an RF
override.

In order for that to happen he needs one positive-going pulse for
the SET input of his 4013, a _separate_ positive-going pulse for the
RESET input, and a CLOCK input from the RF detector. Also, the
4013's Qbar output needs to be connected to the D input, and the
signal from the RF detector needs to be debounced.

I think what I described actually will do what he wants. The set of the
RS latch is from the radio signal, a signal that a reversal of the
normal condition is desired. The reset of the RS latch and a reversion
to normal operation occurs on any day-night or night-day transition,
from a single line that carries a pulse signalling a change of
day/night state. That RS latch is one input to an xor gate, whose other
input is just the day/night condition. The output of that xor gate is
transmitted to the light control. Unless I've misunderstood?

---
If this is what you're advocating: (View in Courier)
_
_| |_
RFDET>--------------A
NOR Y--+
+--B |
| |
| A--+
+--Y NOR
_ | B--+
_| |_ | |
D/N>-------------|--------+---A
| EXOR Y--->OUT
+------------B

then RFDET will only set the latch if it's been previously reset by
a pulse from D/N, which means that you're only allowed one set in
any daylight or dark period. Terry specified that he wanted to be
able to toggle the output with the radio signal which, to me, means
being able to change the output state at will. Like this:
_
_| |_
D>------------------+
|
+------|------+
| | |
| +---+---+ |
_ +--|D S Q|--|--->OUT
_| |_ | | |
RFDET>----------|> 4013 | |
| _| |
| R Q|--+
_ +---+---+
_| |_ |
N>------------------+



Agreed, as per my reply last night.
news:mppt92d1o5njbv9nie7eeroitrqfqkses4@xxxxxxx

--
Terry Pinnell
Hobbyist, West Sussex, UK
.

Relevant Pages

  • Re: Separate pulses from edges?
    ... of a toggle flip-flop. ... Popelish's idea of a single time constant with an xor gate to get both ... change signals on a single line. ... These could be used to reset an R/S ...
    (sci.electronics.design)
  • Re: Separate pulses from edges?
    ... of a toggle flip-flop. ... Popelish's idea of a single time constant with an xor gate to get both ... change signals on a single line. ... These could be used to reset an R/S ...
    (sci.electronics.design)
  • Re: Separate pulses from edges?
    ... of a toggle flip-flop. ... Popelish's idea of a single time constant with an xor gate to get both ... change signals on a single line. ...
    (sci.electronics.design)
  • Re: Separate pulses from edges?
    ... of a toggle flip-flop. ... This being your target, you might use John ... change signals on a single line. ... These could be used to reset an R/S ...
    (sci.electronics.design)
  • Re: spartan 3an application
    ... When this signals is one, you count up and if it's 0 you count down. ... RESET, //input button ... reg Qreset; ... wire PULSE_NEW_out; ...
    (comp.lang.verilog)
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