Re: PCB layout for ADC

On 30 Jun 2006 11:00:44 -0700, "tschoepflin@xxxxxxxxx"
<tschoepflin@xxxxxxxxx> wrote:

Hi everyone

I recently joined a (small) company that has a very high end A/D system
using four 16-bit A/D channels. Two of the channels have a gain of 128
or even more so they can be quite sensitive.

We were using the Burr-Brown DSP102's but they are terribly obsolete so
we are forced to design a "daughterboard" to plug into the through-hole
pins until we finish redesigning the board. We chose the Analog
Devices AD977A as the replacement.

I did not design the original PCB's and that's not my expertise, so I
have a couple of key questions:
1. When connecting the power rails (+5V, -5V, and GND) of the
daughterboard to the main board, should we use only a single pin or
multiple pins? My instincts tell me that we should treat it as a
"star" grounding system and not introduce any loops, so we should only
use 1 pin for each of these nodes. But any thoughts are very welcome.


Use lots of ground pins.

2. We are doing a 4-layer board with GND on layer 2 and the power on
layer 3. For power, we're thinking to do a pour of +5V_analog and then
run thick traces for +5_digital and -5V as necessary. Is this okay or
should we try to do more of a "plane" style with larger areas for the
"minor" rails? BTW, the -5V is not for the A/D, but for an op-amp
buffer that maintains the voltage reference.

Ground plane for sure. Power runs can be fat traces or planes. If
planes, you might put analog planes on the opposite side of the ground
plane from digital power.



3. Any thoughts on doing GND copper pours for the top & bottom layers?
The previous design did not use any copper pours for the routing
layers.

One inner-layer ground plane should be enough. Surface fill-in pours
are mostly cosmetic.


4. The main board already provides "bulk" 10 uF caps for the power
rails. Should we add 10uF caps onto the daughterboard as well or just
not worry about it?

Better to use surfmount ceramics, close to the adc power pins, 0.33 uF
maybe. The ADC ref bypass cap should be local, too.

FYI--we have a single discontinuous clock line running AFTER conversion
at 10 MHz. There is also a CONVST pulse (0.1us wide) to start
conversion. The analog signals range from 30-450 kHz.

Since this ADC has a single-ended input, ground noise is going to be
an issue. If the board is quiet before each ADC shot, that will help a
lot.

We already bought Howard Johnson's "High Speed Digital Design" which is
supposedly the end-all & be-all of PCB layout, but I would say that PCB
layout for A/D's is one of the trickier topics and it's not clear how
to apply those principles to "low speed analog design" :-).

HoJo's book is half good stuff and half nonsense.

John


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