Re: 47uf decoupling caps?!


Tom Bruhns wrote:
rickman wrote:
miso@xxxxxxxxx wrote:
rickman wrote:
He has data that shows that the rule of thumb of 0.1 uF cap per power
pin is way far over kill. In fact, the real high speed decoupling is
done by the power planes alone. The high speed noise can not be
smoothed by the caps simply because of their intrinsic inductance.
Further when they couple with the power plane capacitance, they really
do create a parallel resonance which *increases* the impedance at
certain frequencies.

His approach is to use closely spaced power and ground planes to create
a low impedance path at high frequencies. Then use a few 0.1 caps, a
few more 0.01 caps and a few more 0.001 caps. Of course the smaller
the package the better, but it is important to use parts that do not
have *too low* a value of ESR. The ESR will not affect the performance
of the caps, but it will minimize the peak of the parallel resonances
between all the different parts.

Er, I think the above paragraph needs further elaboration. ;-) I have
seen some sorry LDOs have problems with too low ESR, but geez, bypass
of a digital circuit having a problem with too low ESR?

If you remember your basic AC circuits the paragraph should be self
explanatory. The problem is the parallel resonance which creates an
impedance peak. This can destroy the low impedance of a power
distribution system near the resonance frequency. If you remember that
the shape of a resonance is determined by the resistance in the circuit
which acts to damp resonance, you will realize that you need some
minimum level of ESR in the cap to lower the resonance peak. I have
not found any resources on the web to point you to which demonstrate
this, but the course I took with Lee Ritchey showed this in theory,
simulation and in real measurements.

It is important to remember that the ESR of a capacitor has little to
do with its decoupling ability. It sets the floor at self resonance,
but the remainder of the impedance-frequency plot is determined by the
capacitance and parasitic inductance.

Parallel resonance in power distribution systems is very real.

Indeed. Somewhere recently I read a nice explanation of that, but it's
easy enough to simulate in Spice or RFSim99 or ... If you use two
widely-spaced capacitance values for bypassing, the impedance peak at a
frequency between their series resonances can be rather high. By using
values that are close enough together (such as your suggested 0.1, 0.01
and 0.001uF, or even more different values covering a similarly wide
range), you can control the maximum impedance over a fairly wide range
of frequencies.

What you are doing here makes sense. The smaller caps have less ESR and
ESL, so you are providing some bypass in frequency range where the
large caps have lost their edge due to ESR/ESL. Now granted it is not
much bypass since the cap is small, but it is better than nothing.

The close-spaced power-ground planes are great for the
really high frequencies, as you say. It's also helpful to put those
power and ground planes close to the surface where the parts to be
bypassed are. A via introduces 1/16 inch (1.6mm) of spacing between a
part on one side of the board and a plane on the opposite side. That
can be (almost certainly WILL be) a significant fraction of a
nanohenry, an impedance likely higher than the ESR at even 100MHz.

Note that for a given capacitance, you can lower the Q by either
LOWERING the inductance or RAISING the resistance. Lowering the
inductance has the added benefit of raising the resonant frequency,
allowing better bypassing at higher frequencies. Use parts with lowest
possible inductance; lay out the board with the lowest possible
additional inductance.

Back to the OP's question: I'd say a chip designed to require such
high bypass capacitance is a very poorly designed chip.
In addition,
there is practically NO reason you should have to put that much
capacitance really close to the chip; power fed through an effectively
very low impedance transmission line from a low impedance power supply
at a distance will still look like a low impedance at the chip, even at
low frequencies.

Cheers,
Tom

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