Re: CRT Deflection circuit - sync pulses

On a sunny day (Sun, 05 Nov 2006 21:53:39 GMT) it happened joseph2k
<quiettechblue@xxxxxxxxx> wrote in
<D3t3h.5345$9v5.3328@xxxxxxxxxxxxxxxxxxxxxxxxxx>:

That is actually not correct, in old TV vertical was just a hard synced
blocking oscillator,
And how do you achieve that without the equivalent of phase locking?

Not sure what you mean here, normally the V osc would run slow, here is
a (simplyfied) diagram that I used for example in a design.

----------------------------------------- +12V
| | |
[ ] [ ] R1 [ ]
| | |--------------------------------
| |</ e | |
|---| PNP T1 | T2 |
| |\ c |-- [ ]
T1 | --------\ | unijunction transistor |
| | |-- | T3
| | |------------ B pulse out \| NPN
| |---A | |--===----- V sync
| | | [ ] //|
--->| | === | |
| | | | C1 | |
| | | | |
------------------------------------------------------------------------------ 0V
V hold poti



It _had_ to run slow, so it could be triggered before the restart,
When the V sync causes T3 to conduct the UJT trigger voltage level is slightly lowers, and
it triggers.
The trigger will _coincide_ with the V pulse, so is also phase locked.





and V blanking was derived from the back EMF of the
vertical out,

Not in the sets that i have schematics to. Nor does that invalidate the
fact that vertical blanking is transmitted as part of the NTSC, PAL and
SECAM formats.

Yes, but only in composite video (FBAS).
There is a very simple and obvious reason why it _must_ be so: as the set runs free
(no station) you _still_ want the retrace of H (the flyback) and of V from bottom
to top, suppressed!
It is usually done by pulsing one of the anodes of the CRT with a signal derived from
a tap on the H output transformer, and somewhere from the V, the same circuit will
often also suppress the spot.

I forgot to point out that in modern KTVs the HV cascades (voltage multipliers) have considerable
capacitance too, with plenty of energy to do damage to the phosphors.


Maybe you should read again what the OP posted.
He sort of suggested originally that you could derive the ramp from the
sync pulse. This is possible, but there would be no scan when no sync, and
burn in. There is enough energy when scanning stops in the HV to burn in
the tube before the HV is also gone.
In the very old days when you switched the set off, the picture would
become smaller and smaller, and disappear in a point.

I remember those old sets, with a bright spot in the centre as the anode
voltage decayed, it also spread out as focus voltage decayed which is
partly derived from anode voltage. They did not burn out either.

Yes out of focus helps, normal BW sets had only about 15kV, color sets have
25kV.


Nor did the old TVs from the late 1940s and early 1950s.

Line burn in often happened, I have had a TV repair shop too, repaired thousands (no joking),
and line burn in I have seen too.
Even some old scopes (at about 4kV) had line burn in (remember DG57-34???).

This is true, but incomplete.
As only the leading edge of H is used, no problem making it wider if
composite sync in.

Of equal importance is how much wider? all the way to line time?

Sure, more then half a line and you f*ck up the reverse H in the V in composite.


V-sync is not nearly so straight forward. Google for NTSC and look for a
thorough explanation of vertical sync; to be worthwhile it will include
"equalizing pulses". Now there is a can of worms for you.

Please explain equalizing pulses.


Glad you asked.
We have to look a 3 different cases in case of sync:

1) Composite video (with composite sync).
2) Composite sync, 'S" input.
3) Separate H and V sync inputs (as in VGA 9 pole connector, the OP was talking about originally).

To start with 3 (simplest) most of the time the computer display is not interlaced, and
H and V can just be simple pulses, there need not even be a frequency lock (both derived
from the same clock etc).
And in case of interlace you need no 'egalisation' in fact.

This brings me to your question in case '1' and '2'.
The original reason for the egalisation pulses is dead simple, and almost never mentioned.
The intention was to have the (interlaced) receiver sync separator circuit
_as_simple_as_possible_.

The egalisation pulses are there to make sure the V integrator capacitor is charged in such
a way that the vertical retrace will start at half a line (625 / 2 = 312 1/2 in European PAL).

This system was designed so you could just with a simple differentiator and integrator split the composite sync.

.
.
integrator .
neg polarity R . ramp build up during v sync.
comp sync ----------====-------------- V sync .
| |
| === C
| |
| ///
| |\
| differentiator | \
| | | C ___ __| \_____
-----| |---------------- H sync | /
| | | | /
| |/
[ ] R This edge is used (_also_ in egalisation pulses!)
|
///


It must again be stressed that the comp sync does not need any egalisation pulses if the display
is not interlaced.
maybe some of you will remember the real start of computing, Motorola max-board with 6845 CRT
controller, you just made comp sync by xoring a H pulse with a V pulse.......
And the TV would be nicely locked.
And that twas even a common clock.
I designed a video camera (vidicon) with 2 free running UJTs (as above) as H and V oscillator,
and xored the sync from these, then modulated on CH4 VHF in the sixties!
WAY ahead of everybody :-)
CCTV? I was first and wireless too!
Had it in the garden, battery operated, lasted 20 minute on nicads....


Anyways, TV is a nice subject, have to do somehing now, we can deepen this out if you want to.
Soon the old analog techniques will be forever lost for this generation.
A pity perhaps, as those guys were very inventive really.
.

Relevant Pages

  • Re: CRT Deflection circuit - sync pulses
    ... When the V sync causes T3 to conduct the UJT trigger voltage level is ... but only in composite video. ... Generating a reasonable steady voltage from microsecond wide pulses does ... burn in the tube before the HV is also gone. ...
    (sci.electronics.design)
  • Re: CRT Deflection circuit - sync pulses
    ... and line burn in I have seen too. ... just 'sync'. ... Please explain equalizing pulses. ... And in case of interlace you need no 'egalisation' in fact. ...
    (sci.electronics.design)
  • Re: CRT Deflection circuit - sync pulses
    ... 'LCD" 'burn in' or storage effect, depending on the system and manufacturer ... Please explain equalizing pulses. ... We have to look a 3 different cases in case of sync: ... And in case of interlace you need no 'egalisation' in fact. ...
    (sci.electronics.design)
  • Re: CRT Deflection circuit - sync pulses
    ... no PLL needed. ... But most important is, that if your sync was to interrupt, the scanning ... The time ratio of the H stage is set in the drive circuit. ... pulses were too long/short or at too high/low of a frequency. ...
    (sci.electronics.design)
  • Re: CRT Deflection circuit - sync pulses
    ... I'm not suggesting using a non-locked local oscillator, ... In such a case blanking 'cannot 'wander' if you are in sync. ... and the spot would burn in in the centre. ... sweep and no sweep translates sooner or later to no anode voltage. ...
    (sci.electronics.design)