Re: AD7714 help


Prakruthi wrote:
Prakruthi wrote:
Arlet wrote:
Prakruthi wrote:

I can see constant clock signals on the oscilloscope for SCLK and DIN
and DOUT shows data transfers, but the DRDY acknowledge pin on the
AD7714 sometimes just shows noise and sometimes shows a low(which is
an indication of dataword being available at the output register of the
AD7714) after several several clock cycles.Do you understand what I
mean?

Not sure what you mean. Can you link a picture ?

Also, the SCLK frequency is not constant. It keeps varying. Is that ok?

As long as you're not violating cycle, and setup/hold times of the
AD7714, there's no problem for the communication, but the fact that it
is varying at all sounds suspicious. It *should* be rock solid. Did
you check basics stuff, such as whether your power supply is clean, and
your main oscillator is stable ?

Ya, I have already checked the main oscillator stability.It is rock
solid. The power supply is pretty clean as well. A little noise
occasionally, that should be ok I guess, or?
I was wondering too, why the SCLK frequency was not constant. It varies
pretty drastically sometimes. Im using a SCLK frequency of 115.2 KHz
and sometimes it shoots upto 203.5 KHz. That is quite a lot right.

Unfortunately, I cant link up a picture of the oscilloscope outputs.
But will try to do something. Get a print out and get it scanned or
something.

Thanks again.
WHat do you think is the problem with the SCLK?

I m sorrry, the SCLK is varying because I have some statements in the
program that pull the SCLK high and low after each write and read. When
I eliminated those, the SCLK is in fact rock solid.


I managed to make some changes to the code. And now I see constant data
transfers in MISO and MOSI as opposed to the behaviour earlier.But now
I get a constant output of 3255255 and nothing on the DRDY pin. Any
suggestions?

Prakruthi

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