Re: Any ideas on how to do this?
- From: Tim Wescott <tim@xxxxxxxxxxxxxxxx>
- Date: Sat, 25 Nov 2006 11:22:53 -0800
48 bytes wrote:
Hi everyone!How many clock ticks do you have to do it in?
First of all, thanks for being such a help for like 5 years now.
However, now I'm a serious trouble.
I have to describe and design a 32 bit binary to 40 bits BCD converter.
I'm using VHDL as it's my class' focus language.
I found a very interesting solution at
http://www.engr.udayton.edu/faculty/jloomis/ece314/notes/devices/binary_to_BCD/bin_to_BCD.html
, but when I upgraded it to 16 bits it didn't work as expected.
And imagine having to instance more than 40 of those adders... Even
using the special replication instruction, it would fill the gate
amount of the Xilinx Spartan-3 S3-200, considering that nearly 60% of
it it's being used and I have to maintain that design (a DLX monocycle
processor... Computer Architecture II, geez).
Please, any help on this problem?
Thanks
J.P. Garcia
AKA 48 bytes
You can use the old algorithm of successive divides by ten. If you don't mind using lots of clock ticks you can get the logic size down quite a bit.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Posting from Google? See http://cfaj.freeshell.org/google/
"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html
.
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