Re: Any ideas on how to do this?

On a sunny day (26 Nov 2006 09:46:23 -0800) it happened "Arlet"
<usenet+5@xxxxxxxxxxxxxxxxx> wrote in
<1164563183.193079.51770@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>:

Jan Panteltje wrote:

Not sure here, here is some pseudo code, assuming you have a VGA V sync available:

allocate a spare 32 bits counter
allocate 10 7 bits counters for the decimals
if(negedge Vsync)
{
inhibit main 32 bits counter // do not want a undetermined toggled state
copy counter to spare counter
allow main counter again

spare counter to bcd

add ASCII '0'

// result now ready
result to display RAM.
}

You don't need to inhibit the main counter if you run this code in the
same clock domain as the counter, which I assume is the case. Even if
multiple clock domains are used, the counter can be copied across
without having to stop it.

Hey and I thought I spotted a trouble spot :-)
You are right.
But if different clock domains, is it not so that when you toggle
from say 0x0fff to 0x1000 you may grab for example a state 0x1ff0
depending on how the counter feedback works, and what sort of counter
it is, and related gate delays in any feedback path?
For a simple binary this would likely not be normally the case, but
many postings in comp.arch.fpga about metastability made me stop it?

.

Relevant Pages

  • Re: Any ideas on how to do this?
    ... allocate a spare 32 bits counter ... allocate 10 7 bits counters for the decimals ... You don't need to inhibit the main counter if you run this code in the ... same clock domain as the counter, which I assume is the case. ...
    (sci.electronics.design)
  • Re: Any ideas on how to do this?
    ... allocate a spare 32 bits counter ... allocate 10 7 bits counters for the decimals ... You don't need to inhibit the main counter if you run this code in the ... you can't just copy an N-bit word from one clock domain to the ...
    (sci.electronics.design)
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