Re: Please clarify European resistor value notation for me

On Fri, 08 Dec 2006 17:26:53 GMT, Joerg
<notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote:

Jim Thompson wrote:

On Fri, 08 Dec 2006 17:02:35 GMT, Joerg
<notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote:


Jim Thompson wrote:


On Fri, 08 Dec 2006 08:22:00 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:


[snip]

The debate over US/european/tibetan schematic symbols is silly. We
just make up anything that we like. Why follow rules when you can make
rules?


[snip]

Same here... very human-readable schematics, but netlists are what the
layout guys want.


I became very careful about that. Basically my layouter re-draws the
schematic most of the time. That takes a few extra hours but it's well
invested time.


Sometimes my layout guy recreates a schematic in his tool format...
particularly if he's an employee of the foundry who want their own
documentation.

However I insist of LVS checking against MY netlist ;-)


The pinout on even the most mundane parts such as a BSS123 is not
standard. At first the layouter didn't think so until it did go wrong.
Data*** said 3-1-2, his CAD said 1-3-2. Bzzzzt. What blew me away was
that they even changed it when Siemens became Infineon. IOW there is no
standard.


I don't have that problem... at least not very often... it's rare that
I do a discrete project as I am at the moment.


Well, I can only suggest to watch out. I had several cases where there
was a discrepancy between the schematic of the layouter and his own
layout program. Both being from the same vendor :-(

Where it went wrong the most: SOT23 FETs (mostly n-channel ones), dual
diodes in SOT23, FETs in DPAK. So now I visually check every single type
after the layout.

Between rebending the leads and rotating the part, every possible
SOT-23 layout error can be corrected! Trust me.

John

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