Re: Hysteresis Comparator Methods

"Jim Thompson" <To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx>
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On Thu, 04 Jan 2007 01:11:12 GMT, "Genome"
<mrspamizgood@xxxxxxxxxxx>
wrote:


"John Larkin" <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
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On Wed, 03 Jan 2007 09:15:38 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:

On Wed, 03 Jan 2007 07:57:54 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Wed, 03 Jan 2007 08:21:12 GMT, myrealaddress@xxxxxxxxx
(D from BC)
wrote:

I've seen various hysteresis circuits in app notes such
as:
http://pdfserv.maxim-ic.com/en/an/AN3616.pdf

This appnote is seriously bogus, in that it totally ignores
the
time-domain aspect of the positive feedback. Figure 7 is
especially
pernicious. Unless very carefully thought out, including
consideration
of the slew rate and noise characteristics of the input
signal, the
conventional hysteresis circuit can propagate glitches
contrary to its
claimed bahavior.

This appnote is a great example of simplistic, intuitive
analysis
that's just wrong.


I'm not familiar with this method:

The signal is applied to 2 comparators (no feedback) which
are
connected to a D type latch.
(Longer discription by request.)

One benefit I see is that both comparators can get clean
stable
references.

Anybody familiar with the drawbacks of the 2 comparator D
latch
combo to make a hysteretic comparator?
Is this a vastly superior circuit compared to what's seen
in app
notes?
D

This can be a lot better, because there's no delay coming
back around
into a positive-feedback node, and because the comparator
prop delays
are effectively pipelined... everything flows left-to-
right. The
comparators still have to be well behaved and well
characterized,
specifically to have fairly symmetric rising and falling
edge prop
delays. But this configuration has fewer screwup modes.

The other nice thing here is that the two comparator
references can be
programmed with DACs, allowing thresholds and hysteresis to
be under
software control. I use this configuration in my tachometer
conditioning modules, and it's very flexible.

John


Then there's the optimum method I devised in my MC1650/51
design in
the mid '60's ;-)

...Jim Thompson


Hysteresis internal to ICs can be a lot better, because you
can
localize the positive feedback into a very tight, single-
pole loop.
The HC14 type schmitts are apparently immune from teasing,
too.

Opamps often make better comparators than comparators,
because they
have one dominant pole and don't store as much information
as the
usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis
circuit is
almost universally taught as being a clever thing, taught by
people
who don't understand it.

John


One thing I don't understand is why you Old Blokes bolloxed on
about
comparators with hysteresis and then gave us comparators with
hysterectomies...... and we still have to deal with them.

DNA


The MC1650/51 has BALLS ;-)

...Jim Thompson
--

Oh Great

What's the point of having balls if you haven't got the *** to
deliver it?
I will not mention the sexual aspect of this stuff........ Mr
pico second.

Us thickos want a comparator where we can set the up and down
stuff about
the somewhere else without using our branes.

DNA
..
------------
Talking about picoseconds...
I recently came across this speedy op amp with a hysteresis
control pin.
http://www.analog.com/UploadedFiles/Data_Sheets/ADCMP566.pdf
Interesting but wayyy too fast.
Slower variants are available.
My app specs are 200nS prop delay and 100mV hysteresis.

D

.

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