Re: PLL loop filter design
- From: "Andrew Holme" <andrew@xxxxxxxxxx>
- Date: Sat, 31 Mar 2007 12:32:12 +0100
<ElectricQuadrupole@xxxxxxxxx> wrote in message
news:1175334428.800799.105860@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hello,
I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?
--
Thanks,
Filip.
I normally express open loop gain in terms of the Laplace 's' operator, and
generate Bode plots using SCILAB. I adjust the various parameters, keeping
an eye on gain and phase margins, to optimise performance.
Download SCILAB from www.scilab.org
Try running this script:
c1 = 680e-12;
c2 = 100e-12;
r = 1800;
kvco = 2e6;
kpd = 0.5e-3;
s = poly(0,'s');
f = 1/s/c1 * (1+s*r*(c1+c2)) / (1+s*r*c2);
g = kpd * f * kvco/s;
g = syslin('c', g);
xbasc(0);
bode(g, 1e3, 1e7, .01);
You can also plot closed loop gain, step response and much more.
.
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