Re: PLL loop filter design
- From: John Larkin <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Sat, 31 Mar 2007 10:08:13 -0800
On 31 Mar 2007 02:47:08 -0700, ElectricQuadrupole@xxxxxxxxx wrote:
Hello,
I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?
We recently did this, locking a 40 MHz VCXO to an external 10 MHz
reference. We divided the 40 down to 10, xor'd it with the external
input (both in an FPGA) and used a simple r-c lowpass from the xor
output to the VCXO control input. So the whole phase locked loop costs
a few cents. Just figure out the natural loop unity-gain frequency and
set the r-c rolloff to be, say, 10x that... typically on the order of
a few KHz rolloff for a VCXO. You get a bulletproof first-order loop
and excellent phase noise behavior.
This works because your maximum possible error frequency is small, so
acquisition range is not a problem.
John
.
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- From: ElectricQuadrupole
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