Re: I/O signal conditioning question

In article <24aa13hr24i92b75atebvf53r34nrgl0he@xxxxxxx>,
speffSNIP@xxxxxxxxxxxxxxxxxxxxxxx says...
On Thu, 05 Apr 2007 15:18:51 GMT, the renowned John S. Gaglione
<john.gaglione@xxxxxxxx> wrote:

Greetings Group:
I am working on the interface between an LCD display and
a PIC 16F877A.

The display multiplexes its "BUSY" signal on the same pin as
the 8th data bit.

My problem is that the PIC input pin cannot see the 2.4v BUSY signal.

How do you know it is only 2.4V? What is the LCD display Vdd? What is
the MPU Vdd? Which port are you using for the data bits? Most of the
port pins use TTL-like levels when you use 5V Vdd, but PORTC ohn that
part has ST inputs, and requires 0.8Vdd to see a logic 1. Do you
actually need to read the BUSY signal or can you just use timing?
Most LCD controller chips are CMOS and have outputs that swing from 0V
to VDD.

If I was to make a WAG as to what is wrong, I'd guess that you have
misunderstood the controller data*** and the BUSY output is
open-drain, and thus requires a pullup resistor (something like 10K)
to your Vdd.


I have tried buffering the signal through 2 gates on a 74LS04.
The PIC now can see this fine, but when the LCD switches the pin
over to read data it floats and the '04 gates turn on.
This causes the LCD to read the 8th bit "On" all the time,
interfering with the character data. I tried several
resistors to force the gate input down, but the PIC's data
doesn't get through reliably.

I found that this will work if I connect the signal directly
between the PIC and the LCD, and also connect it to the base
of a PNP transistor with a PCB mount speaker (piezo?),
connected between the Collector and +5, and Emitter to GND.

I don't want to keep the speaker in the circuit, because it seems
to draw a lot of current, and I don't understand why it works.

Any other suggestions for increasing the voltage of my BUSY
signal, without drowning out the signal from the PIC direction?

Thanks

John
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LCD Specs say Vdd +2.4v. Vdd is +5v. Measured on o'scope as 2.4v, so Vdd
+2.4 may be a typo for Vss +2.4. MPU Vdd is +5v, same as LCD.
Data bits to LCD are on port D. I've set TRISE:4 (PSPMODE) to 1, hoping
to get PORTD to be TTL inputs but it still won't see the BUSY signal.
Please pardon my limited electronics knowledge, If I set PSPMODE, with
a 10K pull-up resistor from Vdd to PORTD:7, the "low" level bumps up to
about 2V. With PSPMODE cleared (Schmidt Trigger inputs), the pull-up
does not affect the "low", but raises the "hi" a bit.(2.4v to 2.5v). Is
this the expected behaviour?

Yes, I could ignore the busy signal and just burn cycles to get it to
work, but I want to do it the right way.

With the busy signal connected with the piezo speaker, I sent the display
40 million characters without dropping one. Using timing, I see a
character out-of-place every 5000.

The display is a S28297 made by IEE (Industrial Electronic Engineers)
Inc. from Van Nuys CA. The spec. *** is dated 1983.
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Near N39 40.750 W84 10.408
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