Re: Resources regarding Phase Locked Loops?

Michael wrote:

On Apr 11, 5:11 pm, "RST Engineering \(jw\)" <j...@xxxxxxxxxxxxxxxxxx>
wrote:
My God. My community college engineering TECHNOLOGY students get a full
week of PLL in the second semester of their FRESHMAN year. I'd like to
know, just to avoid, what university are we talking about?

Jim

You have got to be kidding me. Why post such nonsense? Is this some
sort of way to fluff yourself up? An attempt to put others down?
Perhaps a way of compensating for an insecurity about a shoddy
education, or a lack thereof? It's pitiful, sad, and a failure on all
counts.

To answer your question - I attend the 3rd ranked university for EE in
the USA.

I would suggest that your CC is teaching it too early, as there is no
way in hell that they have a strong enough background to understand
how it works at that point. Just having quickly glanced at the math
behind PLLs I can say that. Learning implementation should follow
understanding, in my opinion. I suspect those running your CC feel
differently.

-Michael
Not a lot of ever EE's get to design PLLs. That should certainly make an
elective of the material. ETs often have to troubleshoot PLLs is existing
equipment, that is the difference engineers and technologists. To clarify
it is the difference between having to have the background to analyse it
for design, and having to have a basic understanding of typical industrial
applications and their various uses. Or quickly, between designing the
chip and using the chip.
--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller
.

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