The Education of MassiveProng (Pt 3 of 275) (001/634) (307/634)

bit=1), the three interrupt outputs from FIG. 31 XNOR gates 2692,
2694, 2696 are advantageously routed directly through selector 3810 to
three corresponding predetermined IRQ pins, here IRQ3,4,5. The
Chipsetname Enable bit is bit zero (0) in the Initialization Register
tabulated with the Extension Registers for PCU 112 elsewhere herein.
When this Chipsetname Enable bit is reset by default or by software to
hold a value zero, then the standalone device mode for selector mux
3810 is selected.

The PPU 110 shadows the PCU 112 register locations that define status
.

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