The Education of MassiveProng (Pt 3 of 275) (001/634) (103/634)
- From: MassiveProngSucks. <Massive@xxxxxxxxxxxxxxx>
- Date: Sat, 21 Apr 2007 00:58:35 -0700
FIG. 11 the internal bus 904 is suitably clocked at half or a quarter
of the bus 104 frequency, and higher or lower frequency relationships
are also contemplated.
A bus arbiter 906 on-chip provides arbitration of bus 104 for the MPU
102 of FIG. 5, PPU 110 of FIG. 6, and two external bus masters 210 of
FIG. 7. PPU 110 acts as a bus 104 bus master during DMA cycles for
transfers between bus 104 and a DMA peripheral 910.
One preferred embodiment provides more peripherals that are compatible
with the "PC-AT" architecture. Since the bus 904 provides an on-chip
.
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