Re: Painless micro program

On May 19, 5:54 pm, krw <k...@xxxxxxxxxx> wrote:
In article <1179616199.332790.162...@xxxxxxxxxxxxxxxxxxxxxxxxxxx>,
kensm...@xxxxxxxxx says...
[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

[....]

Not very. Almost every computer keyboard on the planet has an
"8048" in it.

I think today it is more of a 8048 like core in a special chip. I
wouldn't be surprised to see only one package inside a keyboard. With
the kind of quantity they are made in today a special purpose IC makes
a lot of sense.





.

Relevant Pages

  • Re: Accurate(ish) frequency measurement
    ... The simple method - counting cycles - would sort of work. ... clock to measure things more accurately isn't too feasable. ... an interpolator will find Delta_T1 = the time from the active ... edge of the gate to the next active edge of the unknown clock. ...
    (sci.electronics.design)
  • Re: Division by Zero in Nature, and Decomposition of Time.
    ... It *starts* with cycles, historically, but is not ... "the whole universe" to build a clock, ... > they would be either zero or very near zero relative to everything ... > that they simply do not exist relative to an observer such as us. ...
    (sci.math)
  • Re: 8051 architecture
    ... design philosophies from traditional to soft cores fro ASICs. ... Some do run in 2 clock cycles per machine state. ...
    (comp.arch.embedded)
  • Re: On synchronization methods across clock domains
    ... What happens when the dstclk samples some changing bits in one cycle and the rest in the next? ... If your wire foo is used to validate the data is steady for two cycles - which isn't clear since your two_reg_synchronizer module isn't obvious - then this technique actually is recommended. ... You effectively have a slower domain being sampled by a higher speed domain since your srcclk signal lasts 8 clocks. ... I have a source clock, srcclk, which can be as slow as 1000 ...
    (comp.lang.verilog)
  • Re: Need DSP recommendation
    ... > headers etc, the bit banger would have to operate around 1 MHz clock ... Thus, for each sample, the bit banger would have to run 20 ... > cycles, so the number of cycles for bit banging would be less. ...
    (comp.arch.embedded)