Re: PCB Layout Designers

On Wed, 23 May 2007 12:28:20 -0700, "Joel Kolstad"
<JKolstad71HatesSpam@xxxxxxxxx> wrote:

"John Larkin" <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:v01953pbjjde1db2s0up170juovqkro5d4@xxxxxxxxxx
We do the full schematic thing for even the tiniest boards.

I've probably asked before, but what did you say your schematic capture tool
of choice is?

We use PADS-Logic for schematic entry and PADS PowerPCB v5 for layout.
Bugs/crashes are virtually nonexistant. Logic the nicest schematic
editor I've ever used.



We never autoroute, and almost always go with the pins as originally
assigned on the schematic, ie no pin or gate swapping.

Is that because... you're thinking the particular pin or gate used might have
been done so for a reason?

Not really. If we expect congestion (say, a dozen 12-bit ADCs feeding
a big FPGA) we pre-plan the connections before we enter the schematic,
so things flow pretty well. For smaller glue-logic type stuff, our
layout guy seems to just make it work.

In a few recent cases, we told our guy to just use any one of a bunch
of uncommitted FPGA pins, whichever way worked easiest, and let him
handle it. I guess he did hot-wire the connections on the board and
back-annotate the schematic, which is technically not pin-swapping
because there never were any pins to swap! We can finally export the
board netlist and use that to make the FPGA pin constraints file.


In general I find pin and gate swapping of great help, and the guy who entered
the schematic can just set the appropriate attribute if he doesn't want the
pin or gate swapping enabled for the net in question.

We use ORCAD and PADS for production PCBs, but have no path to back-annotate
reference designator changes in PADS back to the schematic (other than doing
it manually, of course).

PADS just does that. When you resequence, it makes a back-ECO file. If
you use Orcad for schematics and PADS for layout, maybe that won't
work.

PADS does, or can do, anything in ASCII. You can export an entire
design in readable ascii form, pcb or schematic, and even include the
library symbols if you like. That lets us look at and process the
files if we want, which is sometimes handy. We've had one or two cases
of weird behavior that were fixed by an ascii export-import cycle.

John


.

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