Re: PCB Layout Designers
- From: John Larkin <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Wed, 23 May 2007 19:47:00 -0700
On Thu, 24 May 2007 09:09:57 +0800, budgie <me@xxxxxxxxxxx> wrote:
On Wed, 23 May 2007 11:26:42 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
On Wed, 23 May 2007 09:23:55 +0800, budgie <me@xxxxxxxxxxx> wrote:
I'm a one-man band when it comes to circuit and pcb design, and I prefer manual
layout (two layers only) over importing a schematic into the pcb software. I
find that:
. package placement is easier without the ratsnest, but with the ability to
have just a selection of interconnections showing.
. the autorouter is great at achieving 85% faster than me, but often fails to
complete and I have to undo sooo much that I haven't used autorouting in the
last five years.
. I have developed a fairly thorough and successful checking process that
hasn't let a layout/connection error through in those five years.
We recently did a board that has over 1000 parts, including a uP and
two FPGAs, 8 layers, parts on both sides. Hand checking that would
probably take two people a week or so, one calling out connections and
the other tracing them. PADS will do a full connectivity check on this
board in about 2 seconds, and a full design-rule check in under 10.
We operate in different worlds, John { ;) >
(snip)
We never autoroute
I wonder how many do autoroute at both your level and down here at the base
where I operate. The tools are there, but I don't think it is ego that stops
most layout people lwetting the autorouter have a go.
Autorouters don't have strategies, like people can, so start at a huge
disadvantage. They often make such a mess of a board that it takes
more time to clean it up than it would have taken to do it manually.
Not to mention the unbearable ugliness most autorouters create.
and almost always go with the pins as originally
assigned on the schematic, ie no pin or gate swapping. We also often
pass the design around from person to person. An engineer may do some
critical placement as a model, our layout guy does the real work, then
another engineer or two may have a final lick at it, checking critical
clock nets and such.
I'm surprised that you don't accommodate gate swapping. Assigning a gate from a
package at schematic time is an arbitrary thing, and can't second-guess which
gate will provide the best layout.
We do usually force sensible package sharing at schematic entry
(proper halves of a dual opamp, say) when that makes sense. We usually
have a rough channel placement or whatever in mind. If we have, say, a
bus connector that goes to a 16-pin bus transceiver, we will assign
the pins that we know will line up nicely. This is *not*
throw-the-schematic-over-the-wall methodology. We'll sometimes meet
and plan a layout strategy, and sometimes change the design if it
looks like that will help.
If my layout guy has a real problem, he can come to us and we can
alter the schematic to help. But on a multilayer board, you don't have
the crossover dilemmas that you have on a 2-sided board, so pin/gate
swapping isn't as crucial.
John
.
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