Re: phase comparator ... > I would like to compare the phase of two 1MHz sinewave and/or ... > squarewave) signals and get a output voltage proportional to their phase ... Is this because an IQ modulator/demodulator..."Phase Lock Loop Circuit Design" by Dan Wolaver is a good book. ... (sci.electronics.design)
phase comparator ... I would like to compare the phase of two 1MHz sinewave and/or ... squarewave) signals and get a output voltage proportional to their phase ...shift, with a small phase angle error ie. 1% if possible. ... Is there a reason why an IQ modulator/demodulator can be made to operate ... (sci.electronics.design)
Re: VHDL Newbie - Is this a valid statement? ... To use a reset inside a design as a control signal is a philosophical question. ... But doing the compare inside your fsm increases the number of inputs unnecessary. ...Comparing signals to constants is very common in VHDL. ... If it's a synchronous reset your counter may stay one count behind the expected value ... (comp.lang.vhdl)
Re: PWM1 & PWM3 synchrounization problem of F2118 DSP!! ... I am setting COMPR1 and COMPR2 to produce two variable-duty cycle PWM... although both signals are having the same period etc. (off ... if i use the same table (compare values) for both ... Is the timer a period register, or is this something perverse like ... (comp.dsp)
Re: PWM1 & PWM3 synchrounization problem!! ... I am setting COMPR1 and COMPR2 to produce two variable-duty cycle PWM... although both signals are having the same period etc. (off course ... with different compare values). ... Is the timer a period register, or is this something perverse like ... (comp.dsp)
