Re: DRAM data persistence

On Jul 3, 7:42 am, MooseFET <kensm...@xxxxxxxxx> wrote:
On Jul 3, 7:07 am, Richard Henry <pomer...@xxxxxxxxxxx> wrote:





On Jul 3, 3:20 am, Iwo Mergler <Iwo.Merg...@xxxxxxxxxxxxxxxxxxxx>
wrote:

Richard Henry wrote:
On Jul 2, 6:30 pm, MooseFET <kensm...@xxxxxxxxx> wrote:
On Jul 2, 4:34 pm, Richard Henry <pomer...@xxxxxxxxxxx> wrote:

I remember years ago hearing about a security problem with DRAM, that
data could partially persist in the DRAM cells through a power-off/
power-on cycle and might be retireved by careful application of power
and reading of the DRAM contents. Does anyone remember details of
this?

I have also seen it happen in static RAM. The data bits are not
accurately remembered but there is a strong bias towards them waking
up in the same state they were at power down.

I guess if someone can have access to the RAM every night after you go
home, they may be able to reconstruct something of what you work on
during the day.

Any suggestions on how to clear the remnants if one does not have the
time to overwrite the whole memory?

Not with generic memory. If you are worried about a security critical
application, the only secret should be a relatively small key, so you
probably don't need to overwrite all memory, just the key storage.

DRAMs are normally specified to maintain storage reliably for 2ms between
refresh cycles. This is of course at the limits of the process, temperature
and voltage ranges. Under less extreme circumstances, the memory can easily
maintain some bits over minutes, even hours. This can be further improved
by getting them down to cryogenic temperatures.

With some SRAMs, there is some sort of burn-in effect, where if the
same content is stored over a long time, there is a slightly over 50%
chance that the bits flip back to this state after a power cycle.

To avoid this, it could help to add a frequently changing random 'salt'
to the key storage. The idea is to store a random number (the salt)
followed by the key which is scrambled with this salt. This doesn't
increase the key security as such, but it avoids the burn-in.

There are special memories for key storage that have asymmetric
SRAM memory cells, which guarantee a specific state at power-on.

If the data were encrypted, there wouldn't be any concern.

This is not true. encrypted data must be decripted to be used. If
that decription happens in software, the RAM that is used by the
software is the target.

I was speaking about my particular problem, not the general case. The
data in the DRAM is not encrypted. The ability to recover the DRAM
contents after a power ccycle will compromise the data.

.

Relevant Pages

  • Re: DRAM data persistence
    ... power-on cycle and might be retireved by careful application of power ... up in the same state they were at power down. ... probably don't need to overwrite all memory, ... chance that the bits flip back to this state after a power cycle. ...
    (sci.electronics.design)
  • Re: DRAM data persistence
    ... up in the same state they were at power down. ... Not with generic memory. ... probably don't need to overwrite all memory, just the key storage. ... chance that the bits flip back to this state after a power cycle. ...
    (sci.electronics.design)
  • Re: DRAM data persistence
    ... and reading of the DRAM contents. ... Not with generic memory. ... probably don't need to overwrite all memory, just the key storage. ... chance that the bits flip back to this state after a power cycle. ...
    (sci.electronics.design)
  • Re: Memory again
    ... address by one cycle, and also serves the function of buffering ... And that is a process typically used on "server" motherboards. ... These are common memory types. ... Always change memory with all power removed from the computer. ...
    (alt.comp.hardware.pc-homebuilt)
  • The Education of MassiveProng (Pt 3 of 275) (001/634) (538/634)
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