Re: Do I need some sort of delay between two latch circuits?

On Fri, 20 Jul 2007 07:41:21 -0700, laylow wrote:

Go buy "The Art Of Electronics".

Yeah, that's the one. Okay, should be here in 3-5 days. If all the
hype about this book is true, blinding light will radiate from my head
after reading it. I'll probably still be back here asking questions
though.

It would also be very helpful to learn to quote context - on USENET, with
a real newsreader, we can only see one post at a time.

Anyway, now that the netiquette is out of the way, lemme see if I got this
straight:

You have Two R-S Latches, and One Clock. In the Default State, RSL1 is
set, and RSL2 is clear; I'm guessing you've got RSL1Q and RSL2Q ANDed
together; and when the clock comes in, you want to guarantee that RSL1
will reset BEFORE RSL2 sets, so that there's no output from the AND.

Is that fairly close?

If so, just take two spare inverters from an HC04 and delay RSL2's "set"
signal. :-)

But, why are you doing this?

Thanks!
Rich


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