Re: Regarding glitches,,,

On Fri, 27 Jul 2007 09:24:24 -0700, Joerg
<notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote:

John Larkin wrote:

On Fri, 27 Jul 2007 00:22:56 -0700, chocka <chocka.pearl@xxxxxxxxx>
wrote:


Dear all,

I need a clarification regarding the glitches in data lines.
I am testing a FPGA prototype board by probing out the data line in
the debug pin of the board and i found that there are many glitches
occured in the data lines on viewing in logic analyser. The data line
is declared as "inout" in our glue logic.
I gave the data line to the 33ohm series termination resistor and
viewing the resistor output in the logic analyser. still the glitch is
coming. I also tried with 22 ohm series termination resistor.Still the
glitch is there...

Any ideas or suggestion please to remove the glitches......

Thanks in advance,


Data busses usually look terrible. They only have to be right at
specific times, and other times they can do anything.


Until you get to the EMC lab for a class B cert ....

If you hire sufficiently clever programmers, all the bus data will be
pseudorandom, spread-spectrum.

John

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