Re: CD4060 oscillator, max resistor value

Joerg wrote:

Hello Folks,

Got a design here that contains a few 4060 long timers with RC
oscillators. Battery operated so consumption counts. Some datasheets
state that the maximum value for any resistor in that area is 1M. Since
Rs (feedback resistor) must be at least twice Rt (timing resistor) this
leads to rather lowish timing resistor values. Since this is a logic
gate oscillator that requirement causes quite some current at voltages
around 10V.

Anyhow, the TI data*** does not seem to state that maximum:
http://focus.ti.com/lit/ds/symlink/cd4060b.pdf

... while ON-Semi does state a 1M maximum:
http://www.onsemi.com/pub/Collateral/MC14060-D.PDF

What gives? Why do some specify that max value as low as 1M for really
low leakage CMOS logic? A remnant from the olden days when this stuff
was leaky at times?

I usually use my own oscillators around CD40106 but this time those are
all used up and there ain't no space no more :-(



I don't think you need to worry about Rs > 2Rt, I think that is just if you
want their frequency formula to work. As long as Rs is "high" I expect it
will still oscillate even if Rs < 2Rt, just at a different frequency.

Anyway I expect that most of your supply current might not be going into
charging/discharging the cap at all, quite likely a lot of current is going
through both the P and N channel FETs in the inverter where its input
voltage slowly approaches the inverter's threshold, and both N and P
channel devices are partly on.

To cure this, my only suggestions are to try not to make the supply voltage
exceed the sum of the N and P channel threshold voltages by too much, or
choose a different kind of oscillator.

You can determine (roughly) the sum of the N- and P channel threshold
voltages by getting an inverter and tying its output to its input, and then
feed the supply pin from a small current source or high value resistor.
Basically an unbuffered inverter with output tied to input is just two
diode-connected devices in series across the supply, and so with a really
low constant current into the supply pin, the input or output pin of the
inverter should be just over the N-ch threshold voltage, and the voltage
between the positive supply pin of the chip and the inverter input/output
will be just above the P-ch threshold voltage. Of course a "buffered"
inverter with its input tied to its output will really contain three
inverters and may not be stable. You might be able to make it stable for
this experiment by putting a big cap to ground on the input and output pins
that are tied together, thus hopefully making a dominant pole.

Chris

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