Re: clock, data, and power on same line?
"Jon Slaughter" <Jon_Slaughter@xxxxxxxxxxx> writes:
Is there any theorical reason why this can't be done?
It has been done. The Dallas/Maxim 1-wire protocol has power, clock,
and data all on one wire.
How?
The line is normally at +5v (providing power, devices have a diode and
cap to maintain it during signalling).
Each falling edge is the "clock" signal.
Each rising edge is the "data" signal - short duration low pulse =
binary 1, long duration = binary 0.
.
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(comp.arch.fpga) |
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