Re: ADC bandwidth and sample rate

Steve wrote:
"David Brown" <david@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message news:46ca8aaa$0$27838$8404b019@xxxxxxxxxxxxxxxxxx
I just noticed an advert for an ADC that runs at 170 MSPS, with a full-power bandwidth of 1.1 GHz. My understanding was that with an ADC at 170 MSPS, you'd want analogue filtering to ensure that no signal above 85 MHz reaches the ADC, since anything higher would be aliased to below 85 MHz. Are these things designed to work with a notch filter of width less than 85 MHz, precisely so that you can properly recover the frequency information after aliasing? Or am I missing something fundamental?

mvh.,

David

You can think of it as a ADC containing an RF mixer. You can down convert < (Sample Clock / 2) MHz wide chunks to baseband as part of the digitizing process. Those chunks of bandwidth can be anywhere up to 1.1 GHz. However, the downconversion will overlay EVERY 85 MHz chunk on top of each other in the 0 - 85 MHz spectrum (assuming 170 MHz clock). The resulting energy is not separable into its original chunks - aliasing is a non linear transformation. So you have to make sure only one chunk actually lands there if you want to be able to make sense of what you have. Hence the need for a very good bandpass filter around the signal of interest. All other signals and noise between DC and >1.1 GHz must be suppressed sufficiently to not be interferers.

This technique is often called undersampling, which gives the impression that it violates the Nyquist rule. It really does not, because Nyquist rule is a bandwidth criterion, not a center frequency criterion. As long as the bandwidth you want to preserve is less than (Sample clock/2), you are OK.

Some caveats to this downconverting technique : 1) the 85 MHz chunks have to be edge aligned on integral multiples of 85 MHz (or sample clock/2). 2) Alternating bandwidth chunks are spectrally inverted (85-170, 255-340, etc). this is not usually difficult to account for in the DSP. and 3) Sample clock phase noise and jitter requirements become more severe with higher input frequencies. Accurately downconverting a chunk from 1020 - 1105 MHz is much harder than 85-170 MHz.

Steve


Thanks for that explanation - you've added a couple of things that I was not sure about, but felt might be a problem (aligning the 85 MHz chunks, and the additional issues as you get higher in frequency compared to your sampling rate).

mvh.,

David

.

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