Re: proper response?

On Sun, 26 Aug 2007 21:24:36 -0400, legg <legg@xxxxxxxxxxxxxxx> wrote:

On Sun, 26 Aug 2007 14:22:00 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Sun, 26 Aug 2007 16:46:45 -0400, legg <legg@xxxxxxxxxxxxxxx> wrote:

On Sun, 26 Aug 2007 08:43:17 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:




We never check gerbers. We do look over the board pretty hard while
still in in PADS, with pretty colors, especially for signal integrity
and mechanical issues. PADS seems to handle connectivity and design
rule checks perfectly, and makes correct gerbers every time.

One issue I've seen with PADS is in schematic entry. What you see is
not necessarily what you get - a trace can appear to be connected,
without sharing the correct net. You have to query every single one to
be sure.

I've never seen that happen. PADS-Logic, unlike some other schematic
programs, simply doesn't allow dangling line segments on a schematic.
You can't draw a line that near-misses another net, and if you delete
any segment of a connection, the entire thing vanishes.

The boards I see are combined linear, digital and power, with
through-hole and SMD. Although I seldom see trouble with elementary
digital gate packages (once the VCC and VSS are defined and manually
assigned), the LSI and multipinned mixed signal devices do allow
overlapping drawn signal ***-ends that are not actually joined.

As well, dots showing a connection may be mislocated back into the
net, or lost underneath another, so that connections that do exist are
not explicit in the rendered schematic - the reverse of my beef.

We must be something procedural around here, perhaps by accident, that
keeps stuff like this from happening. We simply don't have schematics
that are wrong, unless the engineer designs them wrong. I design with
a pencil, on vellum, and my layout guy enters the schematics, and it
just always works.



Schematic 'errors', of course, go through the other processes like
grease through a pig.

The only hazard we see is the strangely-named "signal pins" which are,
in fact, invisible power and ground pins. If a part is created with a
hidden pin named "+3.3V" but you really want to power it from "+3.5V",
from a separate regulator maybe, you've got to check that carefully.


Another issue I have is with drill and pad detail. Firstly, no attempt
is made to produce representative scale drill work in the art - so
you'd best check the DD of the gerbers, if you don't want surprises.
This issue with scale actually applies to the traces and patterns
themselves - so I count on printed gerbers to tell me what the board
vendor will see. Producing different pad art on varying layers, or
thermal relief differing from the default is both error-prone and
frequently impossible, given the choices offered in the GUI.

Again, we don't see a problem here. Traces and pads are shown on the
screen drawn to scale, on all the proper layers, as are drills. We
don't look at gerbers, we don't prototype, we go directly to
multilayer pcb's, and most of our stuff is sellable at rev "A", the
first etch. I can't remember a time when PADS itself caused a problem,
or even crashed.

The problem with scale occurs where it matters the most - at 1:1 or
2:1. Go to higher magnification and it will correctly display
admirable accuracies that may be physically impossible to produce.

At 1:1 and 2:1, rendered art displays resemble actual gerbers like
cartoons represent life study.

PC screens have pixels. That's a problem. If you zoom up on a region
of a board, the actual dims are represented as well as your monitor
allows.


Gerbers more acurately reflect the
errors produced as the vendor reproduces the art using real line
widths - including all artifacts that the PADS program and netlist are
unaware of, and may not bother to dislplay in the selective GUI.

Maybe you've seen these? Drawn circles or squares or other geometric
shaps, solid or filled, coming out of nowhere, without a netlist
association?

Nope.

John


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