Re: How to develop a random number generation device

On Sep 16, 6:16 pm, krw <k...@xxxxxxxxxx> wrote:
In article <1189967601.928633.242...@xxxxxxxxxxxxxxxxxxxxxxxxxxx>,
kensm...@xxxxxxxxx says...

On Sep 15, 11:09 am, John Larkin
<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
[....]
architecture. In a few years we'll have, say, 1024 processors on a
chip, and something new will be required to manage them. It will be a
thousand times simpler and more reliable than Windows.

I think that the number of virtual cores will grow faster than the
number fo real cores. With extra register banks and a bit of clever
design, a single ALU can look like two slightly slower ones.

Not register banks, just a couple of bits in the rename register
files.

I think you mistook my point. You would have as many set of registers
as there are virtual CPUs, perhaps plus some. When a task hits a
point where it needs to wait, its ALU section starts doing the work
for the lower priority task. This could be all hardware so no context
switching time other than perhaps a clock cycle would be needed.


I expect to see multicore machines with less actual floating point
ALUs than actual integer ALUs.

I would think that would be more of a mess than the small amount of
extra hardware for an FPU for each CPU. Asymetries can get messy
fast.

I figure they would form some kind of repeating pattern along the
chip. This way the problems have to be solved only once. The amount
of hardware in a FPU is more than is in the integer ALU and floating
point operations are less common so I think it would work out.

On the later X86 machines there is a second ALU just for doing
addressing. We already have sort of more ALUs than FPUs in the current
machines.

On operations like 1/sqrt(X), doubling the number of transistors can
more than double the speed. You can make the initial guess very good
and loop much less.



--
Keith


.

Relevant Pages

  • Re: How to develop a random number generation device
    ... chip, and something new will be required to manage them. ... a single ALU can look like two slightly slower ones. ... of bits to mark which registers are renamed to which virtual CPUs. ... I dint remember exactly but the FPU I worked on ...
    (sci.electronics.design)
  • Re: problem using FILE pointer
    ... architecture and basic register width are what counts - it was 32-bit ... IMO the ALU width defines the chip, but I won't debate that here. ... how should the 68008 be classified with 8 bit external data bus ...
    (comp.arch.embedded)