Re: SPICEing The Inductance of a Trace Over a Ground Plane?

On Mon, 17 Sep 2007 17:13:47 -0700, "Joel Kolstad"
<JKolstad71HatesSpam@xxxxxxxxx> wrote:

"D from BC" <myrealaddress@xxxxxxxxx> wrote in message
news:fttte3lsufkt3klv2pthl393kdeqtckh8o@xxxxxxxxxx
+ ---------| 13.4pF|----+
| |
+-----////2.98uH///-----+-----------+

The capacitance is to ground, not from one end of the trace to the other.
Also, based on the fact that physical the trace is symmetrical, you often see
people illustrate the network as:

---- L/2 ----
| |
C/2 C/2
| |
---- L/2 ----


or, if you'd like "ground to be ground:"

---- L ----
| |
C/2 C/2
| |
Gnd Gnd

I thought it would be some long repeating LRC network ..

Oh, it is -- eventually. The idea is that, at the highest frequency of
interest for which you except this model to be valid, each LC section should
provide no more than a "small" phase shift where "small" is typically taken to
be 10-30 degrees. It's a useful exercise to compare the frequency response of
a SPICE transmission line element (just a unit delay) with the progression of:

--- L ---
|
C
|
Gnd

--- L/2 -------- L/2 --
| |
C/2 C/2
| |
Gnd Gnd

--- L/3 -------- L/3 ------- L/3 --
| | |
C/3 C/3 C/3
| | |
Gnd Gnd Gnd

...etc...

The idea here is that the *total* inductance and capacitance is the same,
you've just spread it across more and more sections. What you'll find is that
these models behave as reasonably close transmission lines (pure delays) at
higher and higher frequencies as you add sections. In fact, doing this
experiment using physical inductors and capacitors was a popular transmission
lines lab exercise... at least when I was in school!

The above can also be re-cast in terms of digital signals where you typically
make the 10-90% step response time through any one section no more than
perhaps 1/5-1/10th of the input signal's actual rise time.

Another favorite past time (at least before microcontrollers and memory and
ADCs and DACS all became dirt cheap) is to start turning the inductors into
gyrators and try to build long delay lines out of op-amps for use in, e.g.,
audio effect boxes.

---Joel


Ahhh...
So if 10cm of the specified trace on the ground plane equates to
C = 14pF
and
L = 3uH

then using this strip model (transmission line model)
with a pulse gen and load...

pulse > ---- L ------>Hi Z load (CMOS input)
| |
C/2 C/2
| |
Gnd Gnd

...It looks like this can have severe ringing...
Isn't this also called a pie filter..?

Termination or impedance matching (filter dampening?) comes to mind to
stop the ringing.
I guess this is where knowing the solved Zo becomes useful..
I think you posted a characteristic impedance of 47 ohms for this
trace.

So to stop the ringing.. Rsource needs to be 47 ohms and then the CMOS
input needs to be loaded by 47 ohms.

Aside from the 50% signal loss, invalid CMOS levels and a hot pulse
generator...the great is the 10cm strip acts like it's not even
there....if I got that right..


D from BC
.

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