Timing in Synch Comm.
How critical is keeping the timing relatively stable in synchronous
communications? Obviously the slave is synched to the master's clock but is
there ever any problems if the clock timing is extremely unstable? Say
varying up to 10% on average but even peaking to 100% or more in rare
circumstances.
I'm writing a windows app which sends data to the parallel port but because
its pre-emptive there can be extreme latency in the timing. The data is
always synched with the clock so there is no issue with that but just of the
clock's frequency varying a great deal. I imagine since its synchronous
comm. that it should matter but just wondering if there are instances it
could?
Lets say, for example, that its a clock at 1Mhz but then stops completely
for several ms. Could this cause any problem with any device?
I know its the nature of synchronous devices only to send/recv data on a
clock transition and it would seem that frequency variations wouldn't matter
but I just want to be sure that its not going to be an issue.
Thanks,
Jon
.
Relevant Pages
- Re: Spartan 3 clock to output tristate timing
... I'm a stickler for well defined I/O constraints so I see shoddy engineering on the part of the FPGA group, ... The Timing Analyzer within the Xilinx tool suite has a section at the end that summarizes data input setup and hold times as well as clock-to-out for all the various signals. ... I believe the clock and clock edge are included as well. ... As long as the design doesn't budge, ...
(comp.arch.fpga) - Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic -
... "input setup/hold time" is the time required before a clock edge to ... Setup time is the time for the signal to be stable prior to ... live in isolation it is connected to outside devices that may have timing ... the calling module and in the signals used in the submodule. ...
(comp.arch.fpga) - Re: Newbie frustration
... Many times this symptom is a result of a timing violation. ... I need to generate an internal clock:( ... SHIFTp = 13; ... I am using the async FIFO core from Xilinx's coregen. ...
(comp.arch.fpga) - Re: In defence of Austin and Xilinx
... Maximum acceptable jitter is specified in the data sheet but must also be considered *internal* to the device since a poor set of switching I/Os and/or improperly bypassed and distributed rails can affect the amount of jitter seen by the time it gets to the global clock routing. ... A single via can induce 50ps or more of deterministic jitter on a highspeed line, and we won't even get into proper termination or the dozens of other gotchas in timing budget analysis. ...
(comp.arch.fpga) - Re: ddr clock issues
... case xilinx app notes say the timing is adequate so the DQS strobe isn't ... the logic made use of the DQS strobe from the DDR. ... clock that is doubled to run the DDR at 133 MHz. ... the delay in my DCM's to get reliable sampling. ...
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