Re: Confused about synchronous communications


"Jonathan Kirwan" <jkirwan@xxxxxxxxxxxxxx> wrote in message
news:13v5f3h366upnsb2mopthog8etb5vouqcm@xxxxxxxxxx
On Thu, 20 Sep 2007 22:35:15 GMT, "colin"
<colin.rowe1@xxxxxxxxxxxxxxxxxx> wrote:

<snip>
you have to meet set up and hold times,
<snip>

Jon Slaughter? These are the two phrases to get nailed hard into your
head... "set up time" and "hold time." You should look them up, but
in general the idea is that a digital input needs a certain amount of
time while the data is stable __before__ you 'clock it' in -- the set
up time. And, that same input requires a certain amount of time that
you need to keep that same data stable __after__ you clock it -- the
hold time. These surround your clock edge, for edge-triggered inputs.


ok. I had some intuitive idea about didn't know the exact terms. I was
uncertain when the set up time started in the datasheets. I know now though
;)

If you are bit-banging, you can often ignore all if you change the
latching clock edge on a different cpu cycle than you change the data
-- because most of the time your bit banging is way, way slower than
the digital latch its talking to. So I think a lot of programmers
don't even know that it would be a good idea to read a data***, just
do the same old bit banging they've done in the past, and manage to
sneek by in life without getting caught. But in some cases, it can
get you hard.


Yeah, thats why I'm trying to get more information about it. I know I could
just bang them and probably get it to work but I'd know enough about it so I
don't have any anomalous behavior.

Most cpu datasheets will provide some documentation on the worst case
rise time and worst case fall time (often different figures) for their
I/O pins relative to the cpu clock cycle. If you change an I/O pin,
or think you did on some cpu cycle edge, it really takes place some
time later on. If the cpu has multiple clocks per instruction cycle,
it may happen synchronous to that internal clock between instructions,
plus a little analog delay to that. But if you change the clock edge
on a later instruction from the data change, then you are assured of
at least one cpu cycle delay, which is usually more than enough. If
you try and change two I/O pins at once, the data and clock, then you
are probably playing with fire unless you have some reason to believe
otherwise. A delay line on the clock pin, for example, or else that
the data *** of the target device says that the setup time is zero
and puts the setup+hold into its hold time spec because one is
internally delayed relative to the other, perhaps.


I think I do not have to worry about that though? The clock itself will
change 2x as fast and the edge trigger will never change with data because
the data is twice as slow. Basically every other edge will change with the
data but thats not the edge that triggers so its no big deal which one comes
first?

Thanks,
Jon

Jon


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