Re: Confused about synchronous communications

On 9/20/07 3:28 PM, in article
puCIi.8205$JD.5493@xxxxxxxxxxxxxxxxxxxxxxxxxx, "Jon Slaughter"
<Jon_Slaughter@xxxxxxxxxxx> wrote:

I'm trying to implement a general prarallel port communications program but
I'm a little confused about the timing issues involved.

In all of the protocols I'm looking at(I2C, SPI, and ICSP) it seems that the
communications is edge triggered.

What I see is that a data bit is sent when the clock changes and then the
clock changes again.

something like


Data
/---------\
/ \
/ \----



\ /---\
\ / \
\---/ \---/
Clock


So is this normally the case? Also, when does the data have to be valid? On
the second edge transition? (So in some sense the clock is 2x the data rate
so actually the data would be sampled 1/2 inbetween the data transfer rate?)

Basically I'm trying to figure out how I am to write my routine as at the
moment I'm and just changing the clock with the the data but then I realized
that there is no way to keep it synched up perfectly.

I also thought about sorta offseting the clock half way sorta like the above
but with

Data
/---------\
/ \ /
/ \---------/



/---------\
/ \ /
------/ \---------/
Clock

But then this has a problem of the data changing towards the end of the
clock.

So, I guess my actual question is, when is it required for the data to be
valid?

In the synchronous data work I've done, at the business machine interfaces
data is transmitted on the positive going clock edge and it is read during
the negative going clock edge; for each direction of transmission. The data
should be valid for most of the bit-length, but by sampling at the center at
the receiver, any affects from jitter will be essentially eliminated.



Data
/*****-----\
/ \
/ \----



\ /---\
\ / \
\---/ \---/
Clock

Do I have to get "valid data" at **** so that it can be sampled by every
other edge(every rising edge in this case)? If so, is this pretty much how
all synchronous communications works?


Thanks,
Jon



.

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