Parallel port hardware

Does anyone know how the open collector control port in the SPP is

+5
|
4.7 kohm
|
R____|________ TTL input/output
| out
|/
W---|
|\
|
Gnd



I can't seem to find anything that shows how the port is read from and I'm
trying to understand its behavior when reading based on it. The above is
just what I think it probably is but I could be wrong. When reading from
the port W must be 0 and then R follows out. But this isn't quite true
because R seems to latch W to 1 and I have to write W = 0 to allow R to
follow out again.

Basically I'm trying to setup an input and output line into a control port
pin. I read that I have to use all the pins as either input or output but
not mixed? This is probably because I have to reset the pin and I cannot do
them individually? If this is the case then I have to use a status port pin
to read the line when it is working as an input?... which makes it more
complicated.

This is where I'm getting most of my info:

http://www.beyondlogic.org/spp/parallel.htm

and this is specifically where I'm having trouble:

"An external 4.7k resistor can be used to pull the pin high. I wouldn't use
anything lower, just in case you do have an internal pull up resistor, as
the external resistor would act in parallel giving effectively, a lower
value pull up resistor. When in high impedance state the pin on the Parallel
Port is high (+5v). When in this state, your external device can pull the
pin low and have the control port change read a different value. This way
the 4 pins of the Control Port can be used for bi-directional data transfer.
However the Control Port must be set to xxxx0100 to be able to read data,
that is all pins to be +5v at the port so that you can pull it down to GND
(logic 0)."

Not sure why I have to really do all port pins for bi-direction. (Obviously
I can't read and write at the same time but I think I can interleave them to
get what I want)

Any ideas?

Thanks,
Jon


.

Relevant Pages

  • Re: [patch -mm 20/20 RFC] chardev: GPIO for SCx200 & PC-8736x: add sysfs-GPIO interf
    ... We need a standard rep for GPIO in sysfs, ... GPIO hardware design appears to have 2 top-level factors; ... change will also exhibit in the port attr too. ... if a pin is output only, it shouldnt have an _output_enabled attr. ...
    (Linux-Kernel)
  • Re: OT: DOS programming EPP
    ... There seems to be *no* specifications or equivalent circuits for the parallel port as implemented on the ASICs used in modern PCs. ... it is completely unknown as to the maximum safe sink current to a logic low pin or the maximum source current from a logic high pin. ... The EPP page assumes you did. ... CONTROL bit 5 defaults low. ...
    (sci.electronics.design)
  • Re: Any Plug and Play device shuts down PC
    ... Where 'X' represents each pin on the USB header. ... The only other thing that can be done is to adopt the way the rear port on ... if you used a wire ...
    (microsoft.public.windowsxp.hardware)
  • Re: GA4 4-computer Chip .. most advanced ??
    ... from a port with a pin wake-up a data read was required. ... So, the latest intellasys series does not include this (sorry, it is ... Because reading a missing neighbor to access the pin ...
    (comp.lang.forth)
  • Re: bike computer to PC interface
    ... I have a pic of a basic circuit I found but don't know how it works ... Basically it has a connection to pin ... When the com port is opened, ... When the wheel contact was made, ...
    (sci.electronics.basics)