Re: RC Transmission Lines (Wafer-Scale)


"Guy Macon" <http://www.guymacon.com/> wrote in message
news:-YKdnZoXY5mei4faRVn_vwA@xxxxxxxxxxxxxxx



I recently got into a conversation in comp.arch concerning
how fast signals propagate and how far they can travel in
microprocessor wiring.

Some of the posters seem to think that wafer-scale traces/wires
are a lot slower than PWB-scale and system-scale traces/wires
because they are RC transmission lines, not LC.

I did a few crude simulations and it seems to me that the
RC slows down the risetime on single edges and cuts the
amplitude way down on high frequency clock signals, but
I can't see any reason to think that the propagation would
be a lot slower than the usual 60%-80% of C rule of thumb.

I am familiar with normal board and system level transmission
lines such as ECL, stripline, coax, etc., but have never done
any work with chip-scale electronics. Does anyone here know
how fast and how far one can move a signal across a die? Thanks!

--
Guy Macon
<http://www.guymacon.com/>


I can't answer your question directly, but I recently asked a very
knowledgeable Xilinx employee (on comp.arch.fpga) whether their latest FPGAs
used termination techniques for any of their internal signals, and his
response was "yes". So, if this is true (I have no reason to doubt this
particluar individual) then this means that their internal signal edge rates
are fast enough and their path lengths are long enough to warrant the cost
and complexity of on-chip termination (and I'm not talking about their I/O
termination features).

Bob


.

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