Debouncing....at About 1Mhz

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|


Out +------------------------+
| |
A' B'
-------+ +-------------


Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...


D from BC
.

Relevant Pages

  • Re: Debouncing....at About 1Mhz
    ... I need a circuit that triggers on edge A, ... jitter then triggers on edge B and then ignores a following 0.1uS of ... 1>0.1us delay circuit ... your scheme could get a clean, debounced output less than 10 ...
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  • Re: Debouncing....at About 1Mhz
    ... I need a circuit that triggers on edge A, ... jitter then triggers on edge B and then ignores a following 0.1uS of ... 1>0.1us delay circuit ... ...Jim Thompson ...
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  • Re: Debouncing....at About 1Mhz
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  • Re: Debouncing....at About 1Mhz
    ... I need a circuit that triggers on edge A, ... jitter then triggers on edge B and then ignores a following 0.1uS of ... 1>0.1us delay circuit ... ...Jim Thompson ...
    (sci.electronics.design)
  • Re: Debouncing....at About 1Mhz
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