Re: Debouncing....at About 1Mhz

On Thu, 01 Nov 2007 13:25:02 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 15:14:36 -0500, John Fields
<jfields@xxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 12:44:18 -0700, Tom Bruhns <k7itm@xxxxxxx>
wrote:

On Nov 1, 11:17 am, John Fields <jfie...@xxxxxxxxxxxxxxxxxxxxx> wrote:
On Thu, 01 Nov 2007 08:17:25 -0700, John Larkin



<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
On Wed, 31 Oct 2007 21:53:15 -0800, D from BC
<myrealaddr...@xxxxxxxxx> wrote:

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|

Out +------------------------+
| |
A' B'
-------+ +-------------

Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...

D from BC

Looks like you can do it with a dflop, a quad xor, and an RC.

Run the input through a delay-line edge detector (three gates of
delay, then xor) and clock the dflop. Then rc lowpass the input and
apply it to D. Q is the output.

---
???

Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

--
JF

Right, so the xor plus the dflop clock to output needs to have less
delay than that... should be easy with fast parts. The xor is just to
get the same polarity clock pulse from each (leading) clock edge. The
d input is RC delayed, so you capture the "old" level; thus you take Q-
not as the output. RC must be long enough to get past the multiple
transitions at each edge. In fact, you could do it, I think, with an
SR f/f (cross-coupled NANDs) driven from a similar xor nanded with RC-
filtered clock...

---
Something like this?: ;)

news:c56ki3h050okp6mkolm24oq7n67mvmt6rn@xxxxxxx


Or this.

http://s2.supload.com/free/Deglitch.JPG/view/


Total delay is 1 xor plus the dflop. 5 ns shouldn't be hard with
decent cmos parts.

---
No, the clock input is nominally high, so when a new edge comes
along it'll drive the clock input low. Then, after _three_ EXOR
gate delays it'll clock whatever's on D to Q, so the input-to-output
delay will be three EXORs plus one dflop.

BTW, what CMOS parts did you have in mind?


--
JF
.

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