Re: Debouncing....at About 1Mhz

On Fri, 02 Nov 2007 14:44:11 -0500, John Fields
<jfields@xxxxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 02 Nov 2007 11:20:51 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 02 Nov 2007 11:23:12 -0500, John Fields
<jfields@xxxxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 02 Nov 2007 07:14:44 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 02 Nov 2007 04:36:39 -0500, John Fields
<jfields@xxxxxxxxxxxxxxxxxxxxx> wrote:

---
Yup, you're right. I glossed over the delay chain and didn't notice
the grounds. But, there's an even bigger error in that the output
should be Q\ since what's on D will be old data every time clock
goes high and what you want as an output is its complement, as Tom
Bruhns noted earlier, I believe.

There's also the question of input-to-output delay, and looking at
74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and
8.0ns respectively, which doesn't quite meet the 10ns spec. Max
prop delays are 8.5 and 10ns respectively, which is almost twice the
spec.

So, it looks like that, without culling, PECL is the way to go. no?



No.

Modern cmos flipflops have Q and Qbar, so take your pick. They are
fast, too.

---
The point isn't that they have Q and Qbar, it's that you made a
mistake by specifying, verbally and graphically, that the output be
taken from Q.


What the hell is your problem? I suggested a circuit to solve a
problem, for free, and someone else, not you, pointed out that the
output is inverted. It is: So what? Use Qbar or swipe an xor section
and fix it, with my blessings. All you pointed out was that you didn't
understand the clock chain.

My ego isn't invested in this, but apparently yours is.

---
Really? I readily admitted that I made a mistake by glossing over
the clock chain, but you seem to be getting hot under the collar for
having been called to account for committing the same sort (one
would hope) of error regarding the direction of the output.

I'm not hot, and you can't "call me to account" because I don't answer
to you. If you want to keep your private score, go for it.



---

And yes, they're fast, but not fast enough to guarantee an
input-to-output delay of <=10ns without testing the devices for
speed. That is, unless you know of a faster CMOS logic family than
FACT. Do you?

Sure, several. FACT is decades old.

---
Geez, then, instead of all those cutesy pussyfooting tease tactics,
why don't you just give the OP a break and specify what you had in
mind? It is, after all, _your_ design, isn't it? Or does support
not come with it?

It's not a design, it's a suggestion. It doesn't cost anything and it
doesn't come with a warranty.

If you want logic, look at ONsemi, Fairchild, or TI. They have some.

John

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