Re: Debouncing....at About 1Mhz

On Wed, 31 Oct 2007 21:53:15 -0800, D from BC
<myrealaddress@xxxxxxxxx> wrote:

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|


Out +------------------------+
| |
A' B'
-------+ +-------------


Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...


D from BC


Here's what I've finally coughed up... :O *

http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg
547Kb slightly crappy LTSpice screen capture

Notes
------
* Circuit not reduced yet...
* RC values, gate prop, generators will all be adjusted later for
proper timing.
* I chose this timing just to use the default gate parameter
settings..(laziness).
* 1st time doing so much digital in LTSpice... (Most of my digital is
done in CM2000)


Circuit Description
-------------------
D latch A2 latches on 1st positive edge
D latch A1 latches on 1st negative edge

Each latch triggers a one-shot circuit which resets the neighboring
latch.
Each one shot period is just slightly longer than the bounce period.


It looks like it works...

Open to comments or feedback...

D from BC
.

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