Re: Debouncing....at About 1Mhz

On Nov 4, 8:08 am, JosephKK <joseph_barr...@xxxxxxxxxxxxx> wrote:
Tom Bruhns k7...@xxxxxxx posted to sci.electronics.design:



On Nov 2, 10:41 am, D from BC <myrealaddr...@xxxxxxxxx> wrote:
On Fri, 02 Nov 2007 04:36:39 -0500, John Fields

<jfie...@xxxxxxxxxxxxxxxxxxxxx> wrote:
On Thu, 01 Nov 2007 16:33:36 -0700, John Larkin
<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 17:16:19 -0500, John Fields
<jfie...@xxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 13:25:02 -0700, John Larkin
<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 15:14:36 -0500, John Fields
<jfie...@xxxxxxxxxxxxxxxxxxxxx> wrote:

On Thu, 01 Nov 2007 12:44:18 -0700, Tom Bruhns <k7...@xxxxxxx>
wrote:

On Nov 1, 11:17 am, John Fields
<jfie...@xxxxxxxxxxxxxxxxxxxxx> wrote:
On Thu, 01 Nov 2007 08:17:25 -0700, John Larkin

<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
On Wed, 31 Oct 2007 21:53:15 -0800, D from BC
<myrealaddr...@xxxxxxxxx> wrote:

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores
about 0.1uS of jitter then triggers on edge B and then
ignores a following 0.1uS of jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|

Out +------------------------+
| |
A' B'
-------+ +-------------

Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for
edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind
sharing..let me know a topology...

In the meantime, I'll be doodling until I get a
solution...

D from BC

Looks like you can do it with a dflop, a quad xor, and an
RC.

Run the input through a delay-line edge detector (three
gates of delay, then xor) and clock the dflop. Then rc
lowpass the input and apply it to D. Q is the output.

---
???

Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

--
JF

Right, so the xor plus the dflop clock to output needs to
have less
delay than that... should be easy with fast parts. The xor
is just to
get the same polarity clock pulse from each (leading) clock
edge. The d input is RC delayed, so you capture the "old"
level; thus you take Q-
not as the output. RC must be long enough to get past the
multiple
transitions at each edge. In fact, you could do it, I think,
with an SR f/f (cross-coupled NANDs) driven from a similar
xor nanded with RC- filtered clock...

---
Something like this?: ;)

news:c56ki3h050okp6mkolm24oq7n67mvmt6rn@xxxxxxx

Or this.

http://s2.supload.com/free/Deglitch.JPG/view/

Total delay is 1 xor plus the dflop. 5 ns shouldn't be hard
with decent cmos parts.

---
No, the clock input is nominally high,

It is not.

0 xor 0 = 0

1 xor 1 = 0

---
Yup, you're right. I glossed over the delay chain and didn't
notice
the grounds. But, there's an even bigger error in that the output
should be Q\ since what's on D will be old data every time clock
goes high and what you want as an output is its complement, as Tom
Bruhns noted earlier, I believe.

There's also the question of input-to-output delay, and looking at
74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and
8.0ns respectively, which doesn't quite meet the 10ns spec. Max
prop delays are 8.5 and 10ns respectively, which is almost twice
the spec.

So, it looks like that, without culling, PECL is the way to go.
no?

Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway
with the low speed limit.

I'd go for the best that can be done with the 74X series to start.
That <10nS time is based on 1/10th of the total of other delays in
my system. So..It can be relaxed.

I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.
Like driving a bicycle instead of a motorcycle. :(

I can probably do a ultra fast version another day.

D from BC

Just do it in a modern CPLD, and 10nsec should be easy. Though
there's a bit of overhead getting started in CPLDs, it's cool that
when you make a mistake in your logic or see some improvement, it's
just a re-route.

For logic (if you are willing to get away from your SN7474 and
SN7486
parts...), you could use LVC parts at 5 volts. They're fast.

Cheers,
Tom

And waste 99% of the CPLD? We are talking about a task that an old
22V10 is 10X overkill.

Because the OP suggested there is a lot of other stuff in the whole
circuit. Or, if you don't like that answer, "because I like working
with small parts under a microscope." ;-) Though even better,
because I can re-program it with JTAG in-circuit, using the same
programming pod I use for many other parts.

Cheers,
Tom

.

Relevant Pages

  • Re: Debouncing....at About 1Mhz
    ... jitter then triggers on edge B and then ignores a following 0.1uS of ... delay, then xor) and clock the dflop. ... so the xor plus the dflop clock to output needs to have less ...
    (sci.electronics.design)
  • Re: Debouncing....at About 1Mhz
    ... jitter then triggers on edge B and then ignores a following 0.1uS of ... delay, then xor) and clock the dflop. ... so the xor plus the dflop clock to output needs to have less ...
    (sci.electronics.design)
  • Re: Monitoring NTP - nptq -p
    ... My local clock always shows zero delay - is this an assumption that the refclock always has zero delay or is it measured and just too small to display? ... Docs say 'offset of the peer' again in milliseconds. ... A high jitter value would indicate a lot of random noise in the signal, but what can I do if jitter is high? ...
    (comp.protocols.time.ntp)
  • Re: FPGA delay generator
    ... have jitter of some 10s of picoseconds. ... Even with a zero jitter 1GHz clock the generated delay will jitter 1ns. ... SRS generates delay using counters clocked by a crystal oscillator at ...
    (comp.arch.fpga)
  • Re: Debouncing....at About 1Mhz
    ... jitter then triggers on edge B and then ignores a following 0.1uS of ... delay, then xor) and clock the dflop. ... so the xor plus the dflop clock to output needs to have less ...
    (sci.electronics.design)