Re: Debouncing....at About 1Mhz

John Larkin jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx posted to
sci.electronics.design:

On Wed, 31 Oct 2007 21:53:15 -0800, D from BC
<myrealaddress@xxxxxxxxx> wrote:

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS
of jitter then triggers on edge B and then ignores a following 0.1uS
of jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|


Out +------------------------+
| |
A' B'
-------+ +-------------


Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind
sharing..let me know a topology...

In the meantime, I'll be doodling until I get a solution...


D from BC


Here's a single-prop-delay version, which could be done in about 3
ns with one of the tiny-logic parts.

http://s2.supload.com/free/Schmitt.JPG/view/


I probably wouldn't do this in production, because the switch
thresholds of cmos schmitts aren't very tightly defined. My other
circuit is more predictable.

There is likely a variant that uses slow negative feedback that
would be demonstrably reliable but preserves the 1-gate delay.
Haven't worked that one out, but it feels like there's something
there.

John

Would not work in this case. As previously stated signal is from a
comparator.

.

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