Re: Knowledge in DUP-line protocol?

Run.PDP wrote:

Anyone that has deeper knowledge in the DUPline serial protocol?

As to my knowledge, High-level is 8,2 V. Low-level is 2,2V or less
Channel-Generator = Master-Generator by "inactivity" = all bits zero
sends out a continuous sync train, StartOfTransmission pulse =8 ms
of Low, followed by N (32, 64, 128) pulses at time interval 1 ms,
each pulse Low for 0,3 ms, High for 0,7 ms, to describe the 0-signal.

When 1 is transmitted, this is done by reversing the actual pulse, Low
for 0,7 s, High for 0,3 s.

When a device on the bus wants a bit to become 1, it will short the
bus (typical voltage is 0,7V during the short).
This will be noted by the MG / CG, that answers with a regular 1
sequence.

BUT:
How does the MG recognince that someone else wants this bit to become
a 1?
Is it the lowering in voltage ( from 2,2V to 0,7V), or is it the
signal remaining low (like < 4V) during the time of 0,3 - 0,5 ms, ie
when the master tries to make a zero by rizing from Low to High?

So, how long must an external device keep low to set the 1, and when
must
it start?

Best regards,
Göran I Åhling

I assume you're talking about multiplexing devices on the same wire?
if so, all devices should be open-colllector outputs. The master or
some one in the buss must provide the pull up..
Normally, all devices monitor the line for traffic to other devices along with the master. Since all devices are open-collector on TX, the RX is tied to the same line and can monitor it self and others.

No device should attempt to do any TX while a frame time of sequences
are in process.

Is this what you're looking for?


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