Re: Triggering Mosfet with Vgs (2*Vds) > Vds????

Franco wrote:
On Nov 13, 3:32 pm, Winfield <winfieldh...@xxxxxxxxx> wrote:
Franco wrote:
Winfield wrote:
Franco wrote:
I was wondering if there is any inconvenient of triggering
Mosfets (N-Channel BTW) with Vgs twice as big as the Vds???
Not sure what you mean by "any inconvenient," but I can
tell you it's not an uncommon situation, and involves no
unusual difficulties if a supply voltage higher than Vds
is available to power the gate driver.
I meant that I could not find any written material supporting
that way of using the Mosfets. Anyways, if that approach is
usual there should not be any inconvenient. ;)
Do you have any example when to use that configuration?
If you study your written materials, app notes, etc.,
you'll see the issues of Vgs to turn on the MOSFET, and Vds
are independent; there's no relationship between the two.
The most common situation where Vds is much lower than Vgs
occurs when a MOSFET is switched on and Vds is nearly zero.
And of course we expect to use a reasonably-high Vgs voltage,
such as 12V, etc., to insure that the MOSFET is very well ON
in that case. Later, when Vgs = 0 and the MOSFET is OFF,
the drain voltage is free to rise, e.g. up to the Vd supply
voltage, etc, but consider, why should this be very high at
all? For example, the MOSFET might be acting as a rectifier
in a high-current, low-voltage SMPS, delivering 1.8 volts at
60A to a microprocessor. High Vgs voltages are sill required
to turn on the MOSFETs.


It confuses me that there are some curves indicating that
Vds > Vgs - Vth. But, as you mention, the channels (N or P) should
be created independent of the voltage between the terminals.

The mosfets have are commanded by a higher Vgs because I am using
a Brushless Driver motor chip that internally regulates up the
voltages
in the gates for driving the upper mosfets in three half mosfet
bridges.

On the other hand, the voltage being sent to the motor may drop
under the level of that Vgs generated by a bootstrap cap.

Thanks for the answer!


To illustrate Win's point with a real-life example: Take a single fuel cell. It generates about 650mV and an incredible current may be available. However, you cannot really use 650mV directly for anything electronic. So, a few big FETs are arranged, typically in two banks. One bank pulls down one primary, then turns off and now the other pulls the 2nd primary down. Vds is never higher than 650mV.

Those FETs still need 10V or so of Vgs to switch reliably. Mostly those kind of converters generate higher voltages at their outputs but that won't be there without first switching the FETs a few times. Therefore, a little helper oscillator is used that generates 10V or more at low power. This voltage is used to drive an oscillator, the regulator loop and so on. The oscillator feeds buffers and those drive the FET gates hard from 0V to 10V and back.

So here you have it: Vds is between 0V and 0.65V all the time while Vgs is between 0V and 10V.

--
Regards, Joerg

http://www.analogconsultants.com/
.

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