Re: opamp clamp

On Tue, 25 Dec 2007 13:03:33 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 11:50:37 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 12:16:56 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 09:25:16 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 09:28:24 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 08:22:34 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Tue, 25 Dec 2007 08:14:23 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:

On Mon, 24 Dec 2007 14:21:08 -0800, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:


How's this?

ftp://66.117.156.8/Clamp.JPG

I need clean clipping, and can't overdrive some downstream mux's that
run off +5 and ground.

John

http://www.analog-innovations.com/SED/ClampForLarkin.pdf

Would that be clean at 100 KHz? U2 and U3 will wind up hard.

That little detail is left as an exercise for the student ;-)

What does 100KHz mean? Sine or square?

Could be anything; square wave or pulse from a conditioned fuel-flow
sensor; direct signal from a variable-reluctance pickup, mv to 100
volts as speed changes; 120 vac from an alternator. 100 KHz is
probably overkill; a APU turbine is about the fastest thing we'll ever
see, maybe 45 grand, with a pickup on a gear with 32 teeth... 24 KHz
tops.


[snip]

Aha! The real truth erupts ;-) You are only interested in frequency.
So clipping/clamping can be any ol' thing, then run a "charge-pump"
for the tachometer effect.

...Jim Thompson


Analog? Heaven forbid. Downstream, there's switchable lowpass filters,
ac/dc coupling, and an insertable integrator for conditioning
velocity-type sensors. Then two comparators, each with its own
threshold dac. Then into an rs flipflop in an fpga, giving us
programmable trigger levels and hysteresis, then to a semi-slick
period measurement algorithm.

The fpga timestamps rs flipflop rising edges and also counts edges
since the last time it was polled. The uP checks the fpga once every
millisecond. If no edge, skip; if one edge, subtract timestamps to get
period; if multiple edges, subtract timestamps and divide. So above
about 1 KHz, it automagically begins to average multiple periods.
Period data is available every edge, or every millisecond, whichever
is slower.

John



So why the clip/clamp?

You haven't fallen into the "do everything with a uP" crowd have you
?:-)

...Jim Thompson

No, we let fpga's do the heavy lifting, and uP's mostly just move the
results around. Need a half-dozen 32-bit multipliers and a dds
sinewave synthesizer? No problem, they're free.

One of my guys wants to digitize the raw input waveform and do *all*
the subsequent processing in the fpga. I'm not sure I'm ready for
that.


Hey, this ain't bad:

ftp://66.117.156.8/Clipper.jpg

Worked first try, as calculated!


John


.

Relevant Pages

  • Re: opamp clamp
    ... I need clean clipping, and can't overdrive some downstream mux's that ... Downstream, there's switchable lowpass filters, ... The fpga timestamps rs flipflop rising edges and also counts edges ... if multiple edges, subtract timestamps and divide. ...
    (sci.electronics.design)
  • Re: opamp clamp
    ... I need clean clipping, and can't overdrive some downstream mux's that ... Downstream, there's switchable lowpass filters, ... The fpga timestamps rs flipflop rising edges and also counts edges ... if multiple edges, subtract timestamps and divide. ...
    (sci.electronics.design)
  • Re: Intel core 2 quad - faster XMM?
    ... register using AH for some other purpose. ... ECC could get faster IMHO. ... Smarter though would be to have an FPGA in your system coupled to a low ... could plomp it into a multiple processor Opteron board and talk to it ...
    (sci.crypt)
  • Re: Sinewave generation
    ... MHz sine wave in an FPGA? ... I have only limited memory, ... If your target technology has some spare hardware multipliers, ... that's some exact multiple of your 16.758MHz sample rate, ...
    (comp.arch.fpga)
  • Re: FPGA communication, I2C and DAC
    ... inside the FPGA, where I need some advice is how to interface the FPGA ... analog command voltage (multiple channels actually). ... was to use a Cypress PSOC as the DAC and talk between the FPGA and PSOC ...
    (comp.arch.fpga)