Re: fet rise/fall times

Winfield Hill wrote:
Joerg wrote:
Winfield wrote:
Jamie Morken wrote:
I am making a SMPS, and using overkill gate drivers (TC4452
12Amps!!) I have paralleled fets on each leg of the bridges,
not sure if I will try to get away with 1 gate resistor for
all the fets per leg or if its better to use 1 resistor right
at each fets gate. Thanks! :)
One gate resistor per mosfet, that's the rule.
I broke that rule many times. Should I now stand in the corner,
stare at the wall and feel ashamed of myself?

Break it with a high-voltage mosfet and get
20-to-40MHz oscillation as the drains traverse
their voltages.
Depends on what kind of load is hanging off the drain. Also, if you pass
EMI cert with good margins and the FET isn't stressed past any abs max
during these bursts, who really cares?

A good reason to care is the mosfet's health. When
this type of oscillation happens, high voltages can
be developed V = dI/dt on the fet's source bond-wire
inductance, and depending on the osc. frequency and
Ciss, the gate-oxide can be damaged. Goodby FET.
It's happened to me and to others. So it's wise to
avoid the scene entirely, even if the EMI is OK.


At 40MHz that would have to be a lot of inductance. But I can see your point.


Now, as to whether you can sleep at night, worrying
about your paralleled MOSFETs? Who can say?


None of them ever exhibited such oscillation bursts and I tend to test the dickens out of any powerful switcher. Some are in production well over a decade, no problems.

--
Regards, Joerg

http://www.analogconsultants.com/
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