Re: cPLDs and FPGAs we've known and loved (or hated)

Winfield wrote:

What method(s) do you use to design the parts? Thanks!

I'm using VHDL. My latest hobby project was a DDS signal generator with
CORDIC for sine output and a cellular automaton for the random generator,
tested on a Spartan starter kit:

http://www.frank-buss.de/SignalGenerator/

The problem with the fixed clock is high jitter, if the output frequency is
near the clock frequency and if you tune it to e.g. 10.000001 MHz and the
clock is 50 MHz, it output jumps every second instead of a smooth tuning.

Following some links from your homepage I've found this nice synthesizer:

http://seti.harvard.edu/synth/index.html

Using the Analog Devices DDS chip sounds like a good idea. When I have some
time I'll try to use it to generate the clock for the rest of my generator,
which will allow better fine-tuning of the output frequency and reduces the
jitter.

But back to your questions: I've helped a client to develop some VHDL
programs for Cyclone (I and II). Usually I'm drawing some timing diagrams
and flowcharts, then I implement it in VHDL and sometime writing some
testbenches or using the simulator.

I hope I have convinced the teammates to use the simulator more often,
because it can safe time. One example: There is a project which needs some
15 minutes to synthesize. We needed some multiplication for audio
pre-processing, but we have to use the Cyclone I for it, because board
redesign was already finished. So I have implemented a serial multiplicator
(the parallel multiplication built-in needed too many logic elements,
because the part was already very full). With the help of the simulator the
turnaround time was < 30 seconds, which helped me to find some minor bugs
fast (by testing border cases and some random values), before compiling it
with the whole project.

I'm trying some new ideas with VHDL, too. Usually you write multiple
processes to implement a design. Last time I implemented a SPI interface
I've used the "single-process-method" by Mike Treseler:

http://home.comcast.net/~mike_treseler/

It makes the source code more readable, because you don't need to add some
artificial synchronizations between the processes and todays synthesizers
optimizes it very good.

An extension board I helped to develop uses the Cyclone II. We have used
the NIOS soft processor for it and it is very promising: You can just click
together your system-on-a-chip, including many ready to use IP cores and it
is easy to integrate your own VHDL code (with an IO ports interface and
interrupts) and for the small application for which we needed it, the
on-chip BRAM was sufficient. The only drawback is the slow recompile time
with Eclipse (maybe because it uses Cygwin for Windows, which is not very
fast) and some bugs in the tools (there were even bugs in the soft
processor and I can remember a bug in Quartus (not NIOS related), which
generated wrong state machines. Installing the service pack didn't help,
but there was a hot-fix, which patched the service pack, and this solved
the problem).

PS: You should ask this in the comp.arch.fpga newsgroup, which is very
active with many FPGA and CPLD users.

--
Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
.

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