Re: fet rise/fall times

Joerg wrote:
Winfield wrote:
Joerg wrote:
Winfield Hill wrote:
Joerg wrote:
Winfield wrote:
Jamie Morken wrote:

I am making a SMPS, and using overkill gate drivers (TC4452
12Amps!!) I have paralleled fets on each leg of the bridges,
not sure if I will try to get away with 1 gate resistor for
all the fets per leg or if its better to use 1 resistor right
at each fets gate. Thanks! :)
One gate resistor per mosfet, that's the rule.
I broke that rule many times. Should I now stand in the corner,
stare at the wall and feel ashamed of myself?
Break it with a high-voltage mosfet and get
20-to-40MHz oscillation as the drains traverse
their voltages.
Depends on what kind of load is hanging off the drain. Also, if you pass
EMI cert with good margins and the FET isn't stressed past any abs max
during these bursts, who really cares?
A good reason to care is the mosfet's health. When
this type of oscillation happens, high voltages can
be developed V = dI/dt on the fet's source bond-wire
inductance, and depending on the osc. frequency and
Ciss, the gate-oxide can be damaged. Goodby FET.
It's happened to me and to others. So it's wise to
avoid the scene entirely, even if the EMI is OK.
At 40MHz that would have to be a lot of inductance. But I can see your
point.

Now, as to whether you can sleep at night, worrying
about your paralleled MOSFETs? Who can say?
None of them ever exhibited such oscillation bursts and I tend to test
the dickens out of any powerful switcher. Some are in production well
over a decade, no problems.

--
Regards, Joerg

http://www.analogconsultants.com/

Joerg, the oscillation occurs in one to four cycles
of RF during the time the drain voltage is swinging
hundreds of volts, as the FET is transitioning on or
off. It's hard to scope, but if you're very careful
in probe and ground-lead setup, you'll see it on the
source or gate leads. A 10-50MHz wideband RF sniffer
coil can be a useful tool to detect trouble.

That's how I usually check things out, with an EMCO near-field probe
kit. Always been quite, so far. And there have been a few switchers
where I used RF FETs because they happened to be cheaper.

Paralleled high-voltage mosfets without separate gate
resistors and/or ferrite beads are almost certain to
oscillate if the risetime or falltime is long enough
and the current is over 100mA. Consider f = sqrt LC,
and a case with L = 10nH and C = 1000pF, f = 50MHz.
Switching slower than 15 to 25ns without good damping
management can be the beginning of serious trouble.

Ok, I see, but 15-25nsec transitions are considered sluggish in modern
SMPS. Often I use a pnp/npn follower pair to goose things a little.

And I use fairly-powerful mosfet-driver ICs.

Yes, 25ns would be considered slow for a low-
voltage SMPS, but most commercial offline
high-voltage designs that I've examined have
been intentionally kept slower than that. A
360V dc bus being switching in 25ns is doing
15kV/us, which is considered a fast territory.
It seems reasonable that a HV design working
at high enough currents to require paralleled
mosfets would fall into the slower category.

Joerg, you wrote "I broke that rule many times,"
can you say if your paralleled mosfets with a
shared gate resistor, hopefully without trouble,
were one of either: low-voltage, low-current,
or sub-25ns switching designs?
.

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