Re: continuous mode,current mode control, boost circuit

On 23 Feb, 03:23, legg <l...@xxxxxxxxxxxxxxx> wrote:
On Fri, 22 Feb 2008 18:58:20 -0500, legg <l...@xxxxxxxxxxxxxxx> wrote:

Should be dv/dt rather than dv below





No. .A capacitor's voltage changes under the relationship

dv = Ic / C

dv = rate of voltage change (volts / second)
Ic = dq/dt = capacitor current (amps)
C = capacitance (farads)

A simple sinusoidal current will produce it's integral - a cosine -
a similar waveshape delayed 90 degrees.

Complex current waveforms produce complex voltages with identical spot
harmonic content and varying harmonic amplitude (1/f) that are delayed
individually by their own frequency-related 90 degrees shifts.

Becouse the bulk of the current is at double the line frequency, this
double frequency shows up on the LF filter caps.

These are pretty basic concepts covered in most basic electronics
texts.

HF ripple current is created by both the boost source and any HF
switched load. The resulting voltage depends on extent of HF
decoupling and degree of synchronization attempted.

Understand.

Hear is a link to the data*** of the controller:

http://www.fairchildsemi.com/pf/ML/ML4824-1.html
or
http://www.fairchildsemi.com/ds/ML/ML4824-1.pdf

Equation on page 8
Igain=(Iac*veao)/Vrms^2
How would you derive this equation?

I understand that the squared element is a linearization trick, but
cannot seem to grasp the rest.

The text actually reads

Igainmod = [ ( Iac*veao ) / Vrms^2 ] x 1V

<snip>

This is a formula that only applies to this IC in the manner
illustrated in this diagram. Why the term 1/Vrms^2, or 1/Vform^2?
I have to assume it's a 'linearizing' factor introduced to produce a
wider dynamic range in the circuit.

Obviously Vrms shows up in the denominator, as the current requirement
(and hopefully the current limit should reduce as the line voltage
increases, for a constant output power.

I could see this might be raised to an exponent of some kind only if
the current being sensed was a peak value with low continuity. That's
not the case here.

RL- Hide quoted text -

- Show quoted text -

Sorry I'm being a bit slow, and probably not seeing the wood for the
trees.

I understand that there will be phase shifts approaching 90 deg (ESR
makes it not quite 90 deg) because it's a capacitor and basic AC
theory, but the chip is simulating this effect to the line, not the
components themselves, otherwise you wouldn't need the chip. The ac
circuit theory can be used between input and output because the chip
does such a good job of that simulation. What I am trying to find out
is how to plot the mains sinewave input voltage against ripple voltage
using the chips algorithm.

Why does a full wave rectified waveform, turns into what looks like a
good sinewave? This waveform is what is confusing me. I think it is
too pure to be power parasitic elements and have a hunch that it's
something to do with the control chip. I may be wrong it won't be the
first time!

I think this formula is the key.

Igainmod = [ ( Iac*veao ) / Vrms^2 ] x 1V

How in words does this help to achieve unity power factor?

Obviously Vrms shows up in the denominator, as the current requirement
(and hopefully the current limit should reduce as the line voltage
increases, for a constant output power.

Doesn't the current sense pin do this function by scaling the output
of the modulator signal? This chip has a cycle by cycle current limit
and thus power limit and in any case this Vrms provides a long term
voltage signal as it's slow, because it's heavily filtered.

From what I understand (limited I know) Pin 2 Iac is the instantaneous
input current and is bouncing up and down in a full wave rectified
kind of way. This signal provides an accurate scaled current, so the
chip has a reference to which it can use to draw current in phase
with.

Iac is then modulated with the voltage loops error signal (probably to
inject output voltage level information and provide some line phase
information to the signal at that point), in effect providing a
reference for the current error loop.

Isn't the 1/Vrms^2 term to provide feed forward to keep the slow
voltage control loop from having to react to changes in line voltage?

I'm not too clear yet and need to find an explanation in words for how
this form of active PFC works. I don't think the description in the
document from the manufacturer fully explains the equation above.

I need waveforms!!

Any ideas?

Confused Reggie...
.