Re: Capacitor Discharging with CMOS Gate



John Larkin wrote:
On Mon, 25 Feb 2008 11:56:24 -0500, Fred Bloggs <nospam@xxxxxxxxxx>
wrote:



John Larkin wrote:

On Mon, 25 Feb 2008 08:15:16 -0500, Fred Bloggs <nospam@xxxxxxxxxx>
wrote:



John Larkin wrote:


On Sat, 23 Feb 2008 10:11:50 -0500, Fred Bloggs
<nospam@xxxxxxxxxx> wrote:




John Larkin wrote:




Recently, one of my better customers started blowing up Tiny
Logic tristate buffers that can gate a clock out to a
connector on one of our VME modules. They never enable the
output function, and only apply +3 dBm RF to the connector as
an input, so we can't imagine how the chips fry. You can tell
the dead ones by the tiny bubble of charred conformal coating
on top the SOT-23 package. We tried every sort of abuse we
can imagine and can't zap them here. After a zillion meetings
and conference calls, we decided to remove the chip.


Are you saying these buffers are off a bidirectional port on
your module and the customer is applying a 3dBm clock to it?
How is this terminated for input mode drive?


Bandpass filter and comparator, as noted elsewhere.

Oooooh yeah- almost guaranteed to blow the sig gen...




Yeah, not many sig gens can handle a load like this...


in (o)------------470r-----+-------+---------comp+ |
| | gnd | | +---comp- L C
| | | | | | gnd | | gnd gnd


Terrifying, just terrifying.


John



Is that 470R or 47R, either way,


Our convention is that 470r means four hundred and seventy ohms.


I know of at least one fairly popular
lab grade type that would not like that at all...you should have used a constant impedance filter. See the tutorial in US6608536, know-it-all.


You know of a generator that blows up when it drives a 470 ohm load?
Let me know, so I'll be sure to not buy one.

Oh, the reason to keep the input impedance high is so that one 10 MHz
source can lock a lot of modules. The bandpass/comparator makes the
thing pretty much indifferent about waveforms.

John


Okay- well that's not the best way to do it. I never had any problem with a JFET compound follower with hardwired 1MR pulldown from gate to gnd for a daisy chained drive, and a switchable 56R for proper relatively broadband termination as required. Then follower into a series resonant bp R+L+C controlled Q around 20 or so.

.

Relevant Pages

  • Re: Capacitor Discharging with CMOS Gate
    ... John Larkin wrote: ... Logic tristate buffers that can gate a clock out to a ... connector on one of our VME modules. ... your module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... tristate buffers that can gate a clock out to a connector on one of ... our VME modules. ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Tuning a crystal to another one?
    ... It seems all I'd need is some sort of analog sampling gate that fires ... It's a 16MHz clock. ... to have a constant duty cycle (or at least a duty cycle that doesn't ... enough--that the reference signal is at a lower frequency.) ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... tristate buffers that can gate a clock out to a connector on one of ... our VME modules. ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)
  • Re: Capacitor Discharging with CMOS Gate
    ... one of my better customers started blowing up Tiny Logic ... tristate buffers that can gate a clock out to a connector on one of ... apply +3 dBm RF to the connector as an input, ... module and the customer is applying a 3dBm clock to it? ...
    (sci.electronics.design)