Re: High Precision Monostable


"John Larkin" <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
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On Wed, 12 Mar 2008 04:31:04 GMT, "Jure Newsgroups"
<jure@xxxxxxxxxxxxxx> wrote:


"John Larkin" <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in
message
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On Tue, 11 Mar 2008 16:06:48 GMT, "Jure Newsgroups"
<jure@xxxxxxxxxxxxxx> wrote:


"John Larkin" <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in
message
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On Tue, 11 Mar 2008 04:15:10 -0700 (PDT), sergio108
<sergio108@xxxxxxxxx> wrote:

Hi All.
We are working on a project where we need a very stable monostable to
produce 5 microsecond pulses every time an input pulses arrive. We
have tried IC 74123 and 74221 integrated circuits but the pulse width
is not stable enough. Does anyone know a circuit or integrated circuit
that produce high stable pulse width?. We need 5 microsecond pulses +-
0.01%. Actually we work in a range from 1 to 10 microsecond pulse
width.
Thanks for your help or advice.
Sergio


0.01% of 5 us is 100 PPM, namely 500 picoseconds. That's not the sort
of stability you'll get from simple one-shot type circuits, or even a
precision ramp/comparator. If you don't mind the initial output edge
being synchronized to a clock, you could do this with a counter, with
maybe a small additional analog delay to interpolate between clock
ticks... but it will still be a challenge to hold 500 ps over
temperature, and to keep the pulse-width jitter down.

This will easily do it, but it's not cheap:

http://www.highlandtechnology.com/DSS/T560DS.html

What's the project?

John



Sergio,

a possible solution is to implement more or less a time to digital
interpolator
"backwards", (to deal with the async input).

0) there is a stable enough (...?) clock running at, say 100 MHz ( T=
10
ns)

1) an async input trigger signal
a) triggers a discriminator ( constant fraction ...?)
b) starts an analog integrator
c) sets the output

2) the integrator is stopped and held at its value,
on the next active edge of the 100 MHz clock

3) a counter runs for an integer number of periods of the clock

4) on the finalization of a prescribed count N,
the integrator is restarted from where it was stopped in 2)

5) the integrator runs until a comparator detects a voltage equivalent
to T=10 ns

6) the output is reset

thre are a lot of fine details left for the dedicated reader to deal
with...

good luck !

Jure Z.



That's similar to the way the SRS DG535 delay generator works. The
trigger is run into a clocked dual-rank syncronizer, basically a 2-bit
shift register. It produces a pulse that's between 1 and 2 clocks
wide, which drives a holdable analog ramp. Then they tick off N clocks
and go into another analog ramp as the fine delay. The voltage from
the input ramp is added to the target voltage of the output ramp,
theoretically cancelling the input trigger-to-clock jitter. It
involves a lot of analog storage, but works fairly well for short
delays. Any errors in matching the ramp slopes become jitter. They run
at 80 MHz, I seem to recall.

The Signal Recovery delay generator uses the fiendishly clever
Pepper-patent interrupted ramp technique, much simpler.

John


good idea John,

http://www.google.com/patents?id=HlsfAAAAEBAJ&dq=4968907

Patent number: 4968907
Filing date: Nov 19, 1987
Issue date: Nov 6, 1990

Abstract
An improved digital delay generator (10) for producing an output
pulse/signal a preselected time interval after an input pulse/signal. The
digital delay generator (10) of the present invention includes a single
auxiliary timer (24) which starts responsive to feeding an input pulse
thereto....

thanks , Jure Z.




The patent is a little obscure. The idea is to make a simple
constant-current-capacitor-comparator ramp type delay, with a dac
driving the other side of the comparator, to make a delay from, say, 0
to 50 ns. That's simple. The trick is that one can then stop the
current source for N clocks of a crystal oscillator, 50 MHz maybe,
wait out any number of ticks, then resume and finish the timing. The N
clocks of no-current extend the delay precisely (put a flat in the
ramp) but add no jitter.

The problems are mostly analog: charge injection, leakage, things like
that. But it's simple and has a lot of nice properties.

John


John,
I admit to not being aware of the Pepper patent until you
mentioned it. What I suggested in my post was exactly an
interrupted ramp generator.

As you mnetion, the issues are related to : the integrator switching
states ( integrate/hold/reset ), integrator errors such as droop or
offsets in the hold mode, discriminator switching jitter, prop delays
through logic and drivers, etc.

To the extent that these errors are constant with time, temp,
operating
conditions, they imply a bias (offset) in the produced time
interval.

The potentially nasty situation is when the trigger signal comes
synchronously with the local oscillator active edge, and the system
may add ( or swallow) a whole clock period. That's why the
synchronizers are needed.


Thanks, Jure Z.

PS : where is the OP , while we talk about "his" problem ?




.

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