Re: Variable amplitude clock?



Joerg wrote:
Fred Bloggs wrote:



Joerg wrote:

jdhar wrote:

Thanks Fred, I was looking for an IC like this for some time, but
couldn't find it! I nee to drive a High-Z load, so I think this may
work if I vary the supply. Most ICs I found couldn't go this low in
Voltage.

On Mar 17, 12:24 pm, Fred Bloggs <nos...@xxxxxxxxxx> wrote:

I have a project where I need to design a clock circuit that has
variable amplitude (from ~1.2V - 3.3V). The input clock to this
variable gain stage would be 3.3V, but I have to be able to scale it
down to 1.2V if necessary. Digital control of the gain would be nice,
but not necessary. The clock would need to be ~50Mhz max.
Some options I was thinking of...
- Opamps/variable gain amplifiers come to mind, however, I don't think
they would work well with square waves - would they?
- I could maybe use discrete FETs and use an independent voltage
supply to the FETs that I can program digitally
- Using a high-speed DAC would be good, but I'm not sure if jitter
would be a problem here. WIth a DAC, I could control the high and low
levels precisely, which seems to be the best solution... rise and fall
time maybe an issue to.
Does anyone know how this is typically done with function generators
etc?


Who the hell knows how it's "typically done with function generators
etc"- you could try something like this, but it's getting close hitting
50MHz at the low voltages, will depend on your loading. Have you omitted
a minor detail like it's supposed to be a 50R driver, if so then back it
up with a standard series terminated video amp:
View in a fixed-width font such as Courier.

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. Vamp>--------+-||--.
. | |
. | ---
. | com
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. CLK >------| >------>VAR_AMP_CLK
. 3.3V |/
. LOGIC | 74AUP1G34
. |
. --- MOS gate with overvoltage
. /// tolerant inputs
.
.http://www.standardics.nxp.com/products/aup/data***/74aup1g34.pdf
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If you do that add a resistor in series with the input in order not to exceed the substrate diode abs max ratings. And don't let Jim Thompson see that ;-)


That's NOT how overvoltage tolerant logic works!


If it's a level translator, ok. But the data*** only says 3.6V I/O tolerant, not much more info other than a substrate diode 50mA abs max:

http://focus.ti.com/lit/ds/symlink/sn74aup1g34.pdf

I wish they would give as much info as they used to in the good old days, with a circuit diagram ans such.

See document page 4. in http://www.standardics.nxp.com/support/documents/logic/pdf/an10156.pdf

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